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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

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This commit is contained in:
Blaise Tine
2020-11-02 01:50:12 -08:00
parent 3fe31fc337
commit 5be1d85648
39 changed files with 1145 additions and 1322 deletions
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4
hw/rtl/libs/VX_fair_arbiter.v
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@@ -52,8 +52,8 @@ module VX_fair_arbiter #(
.N(N)
) priority_encoder (
.data_in (requests_use),
.data_out (grant_index ),
.valid_out (grant_valid )
.data_out (grant_index),
.valid_out (grant_valid)
);
always @(*) begin

2
hw/rtl/libs/VX_generic_queue.v
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@@ -3,7 +3,7 @@
module VX_generic_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 1,
parameter BUFFERED = 0,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
) (

7
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -8,21 +8,18 @@ module VX_priority_encoder #(
output wire valid_out
);
reg [`LOG2UP(N)-1:0] data_out_r;
reg valid_out_r;
always @(*) begin
data_out_r = 0;
valid_out_r = 0;
data_out_r = 0;
for (integer i = 0; i < N; i++) begin
if (data_in[i]) begin
data_out_r = `LOG2UP(N)'(i);
valid_out_r = 1;
break;
end
end
end
assign data_out = data_out_r;
assign valid_out = valid_out_r;
assign valid_out = (| data_in);
endmodule