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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

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This commit is contained in:
Blaise Tine
2020-11-02 01:50:12 -08:00
parent 3fe31fc337
commit 5be1d85648
39 changed files with 1145 additions and 1322 deletions
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6
hw/rtl/VX_execute.v
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@@ -38,6 +38,7 @@ module VX_execute #(
VX_fpu_to_cmt_if fpu_commit_if,
VX_exu_to_cmt_if gpu_commit_if,
input wire busy,
output wire ebreak
);
@@ -69,11 +70,12 @@ module VX_execute #(
.clk (clk),
.reset (reset),
.cmt_to_csr_if (cmt_to_csr_if),
.csr_to_issue_if (csr_to_issue_if),
.csr_to_issue_if(csr_to_issue_if),
.csr_io_req_if (csr_io_req_if),
.csr_io_rsp_if (csr_io_rsp_if),
.csr_req_if (csr_req_if),
.csr_commit_if (csr_commit_if)
.csr_commit_if (csr_commit_if),
.busy (busy)
);
`ifdef EXT_M_ENABLE