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Add modified RTL files for parameterized builds with VX_define_synth.v

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wgulian3
2020-03-20 04:04:15 -04:00
parent ff2fc5fa43
commit 5b3df797a4
5 changed files with 29 additions and 17 deletions
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2
.gitignore vendored
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@@ -4,3 +4,5 @@
./rtl/modelsim/*.vcd ./rtl/modelsim/*.vcd
*.vcd *.vcd
.* .*
*.pyc
__pycache__

2
rtl/Makefile
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@@ -9,7 +9,7 @@ MULTI_CORE=Vortex_SOC.v
EXE=--exe ./simulate/test_bench.cpp EXE=--exe ./simulate/test_bench.cpp
MULTI_EXE=--exe ./simulate/multi_test_bench.cpp MULTI_EXE=--exe ./simulate/multi_test_bench.cpp
COMP=--compiler gcc COMP=--compiler gcc --language 1800-2009
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO= # WNO=

18
rtl/VX_define.v
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@@ -125,9 +125,6 @@
-199 -199
`define NUMBER_CORES_PER_CLUSTER 2
`define NUMBER_CLUSTERS 1
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
// `define SINGLE_CORE_BENCH 0 // `define SINGLE_CORE_BENCH 0
@@ -135,8 +132,6 @@
// ========================================= Dcache Configurable Knobs ========================================= // ========================================= Dcache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes
`define DCACHE_SIZE_BYTES 1024
// Size of line inside a bank in bytes // Size of line inside a bank in bytes
`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
@@ -156,9 +151,9 @@
// Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size // Core Request Queue Size
`define DREQQ_SIZE `NT*`NW `define DREQQ_SIZE `NW
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`define DMRVQ_SIZE `DREQQ_SIZE `define DMRVQ_SIZE (`NW*`NT)
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`define DDFPQ_SIZE 2 `define DDFPQ_SIZE 2
// Snoop Req Queue // Snoop Req Queue
@@ -188,8 +183,6 @@
// ========================================= Icache Configurable Knobs ========================================= // ========================================= Icache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes
`define ICACHE_SIZE_BYTES 1024
// Size of line inside a bank in bytes // Size of line inside a bank in bytes
`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
@@ -294,8 +287,6 @@
// ========================================= L2cache Configurable Knobs ========================================= // ========================================= L2cache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes
`define LLCACHE_SIZE_BYTES 1024
// Size of line inside a bank in bytes // Size of line inside a bank in bytes
`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
@@ -315,9 +306,9 @@
// Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size // Core Request Queue Size
`define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTER) `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`define LLMRVQ_SIZE `LLREQQ_SIZE `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`define LLDFPQ_SIZE 2 `define LLDFPQ_SIZE 2
// Snoop Req Queue // Snoop Req Queue
@@ -345,7 +336,6 @@
// ========================================= L3cache Configurable Knobs ========================================= // ========================================= L3cache Configurable Knobs =========================================
// `define L3C 1
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`define L3CACHE_SIZE_BYTES 1024 `define L3CACHE_SIZE_BYTES 1024

16
rtl/VX_define_synth.v
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@@ -1,7 +1,21 @@
`ifndef VX_DEFINE_SYNTH `ifndef VX_DEFINE_SYNTH
`define VX_DEFINE_SYNTH `define VX_DEFINE_SYNTH
`define NT 2 `define NT 4
`define NW 8 `define NW 8
`define NUMBER_CORES_PER_CLUSTER 2
`define NUMBER_CLUSTERS 1
`define DCACHE_SIZE_BYTES 4096
`define ICACHE_SIZE_BYTES 1024
// L2 Cache size
`define LLCACHE_SIZE_BYTES 8192
// `define QUEUE_FORCE_MLAB 1
// Use l3 cache (required for cluster behavior)
// `define L3C 1
`endif `endif

8
rtl/VX_generic_queue_ll.v
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@@ -1,3 +1,4 @@
`include "VX_define_synth.v"
module VX_generic_queue_ll module VX_generic_queue_ll
#( #(
@@ -24,7 +25,12 @@ module VX_generic_queue_ll
assign full = 0; assign full = 0;
end else begin end else begin
(* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0]; `ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0];
`else
reg[DATAW-1:0] data[SIZE-1:0];
`endif
reg[DATAW-1:0] curr_r, head_r; reg[DATAW-1:0] curr_r, head_r;
reg[$clog2(SIZE+1)-1:0] size_r; reg[$clog2(SIZE+1)-1:0] size_r;
reg[$clog2(SIZE)-1:0] wr_ctr_r; reg[$clog2(SIZE)-1:0] wr_ctr_r;