merging changes from OPAE branch making this branch
This commit is contained in:
Blaise Tine
70
old_rtl/quartus/Makefile
Normal file
70
old_rtl/quartus/Makefile
Normal file
@@ -0,0 +1,70 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.v
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Part, Family
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N4F45I3SG
|
||||
|
||||
# Executable Configuration
|
||||
SYN_ARGS = --read_settings_files=on
|
||||
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
|
||||
ASM_ARGS =
|
||||
STA_ARGS = --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt
|
||||
|
||||
syn: smart.log $(PROJECT).syn.rpt
|
||||
|
||||
fit: smart.log $(PROJECT).fit.rpt
|
||||
|
||||
asm: smart.log $(PROJECT).asm.rpt
|
||||
|
||||
sta: smart.log $(PROJECT).sta.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES)
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
||||
fit.chg:
|
||||
$(STAMP) fit.chg
|
||||
|
||||
sta.chg:
|
||||
$(STAMP) sta.chg
|
||||
|
||||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox
|
||||
30
old_rtl/quartus/VX_gpr_syn.qpf
Normal file
30
old_rtl/quartus/VX_gpr_syn.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||
# Date created = 00:18:19 September 11, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.0"
|
||||
DATE = "00:18:19 September 11, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "VX_gpr_syn"
|
||||
63
old_rtl/quartus/VX_gpr_syn.qsf
Normal file
63
old_rtl/quartus/VX_gpr_syn.qsf
Normal file
@@ -0,0 +1,63 @@
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
|
||||
set_global_assignment -name FAMILY "Arria 10"
|
||||
set_global_assignment -name DEVICE 10AX115N4F45I3SG
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn
|
||||
set_global_assignment -name SEARCH_PATH ../
|
||||
set_global_assignment -name VERILOG_FILE ../VX_define.v
|
||||
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_alu.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_decode.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_execute.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_memory.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_warp.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
|
||||
set_global_assignment -name VERILOG_FILE ../Vortex.v
|
||||
set_global_assignment -name SDC_FILE vortex.sdc
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
1
old_rtl/quartus/asm.chg
Normal file
1
old_rtl/quartus/asm.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
old_rtl/quartus/fit.chg
Normal file
1
old_rtl/quartus/fit.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
old_rtl/quartus/map.chg
Normal file
1
old_rtl/quartus/map.chg
Normal file
@@ -0,0 +1 @@
|
||||
Wed Sep 11 00:18:22 2019
|
||||
88
old_rtl/quartus/project.tcl
Normal file
88
old_rtl/quartus/project.tcl
Normal file
@@ -0,0 +1,88 @@
|
||||
package require cmdline
|
||||
|
||||
set options { \
|
||||
{ "project.arg" "" "Project name" } \
|
||||
{ "family.arg" "" "Device family name" } \
|
||||
{ "device.arg" "" "Device name" } \
|
||||
{ "top.arg" "" "Top level module" } \
|
||||
{ "sdc.arg" "" "Timing Design Constraints file" } \
|
||||
{ "src.arg" "" "Verilog source file" } \
|
||||
}
|
||||
|
||||
array set opts [::cmdline::getoptions quartus(args) $options]
|
||||
|
||||
project_new $opts(project) -overwrite
|
||||
|
||||
set_global_assignment -name FAMILY $opts(family)
|
||||
set_global_assignment -name DEVICE $opts(device)
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
|
||||
|
||||
set_global_assignment -name SEARCH_PATH ../
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../VX_define.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../VX_alu.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_decode.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_define.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_execute.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_memory.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_warp.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
|
||||
set_global_assignment -name VERILOG_FILE ../Vortex.v
|
||||
|
||||
set_global_assignment -name SDC_FILE vortex.sdc
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
project_close
|
||||
|
||||
# set_global_assignment -name VERILOG_FILE $opts(src)
|
||||
|
||||
27
old_rtl/quartus/smart.log
Normal file
27
old_rtl/quartus/smart.log
Normal file
@@ -0,0 +1,27 @@
|
||||
Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Shell
|
||||
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||
Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and its AMPP partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel FPGA IP License Agreement, or other applicable license
|
||||
Info: agreement, including, without limitation, that your use is for
|
||||
Info: the sole purpose of programming logic devices manufactured by
|
||||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details.
|
||||
Info: Processing started: Wed Sep 11 00:18:22 2019
|
||||
Info: Command: quartus_sh --determine_smart_action VX_gpr_syn
|
||||
Info: Quartus(args): VX_gpr_syn
|
||||
Info: SMART_ACTION = SOURCE
|
||||
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
|
||||
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 687 megabytes
|
||||
Info: Processing ended: Wed Sep 11 00:18:22 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
1
old_rtl/quartus/sta.chg
Normal file
1
old_rtl/quartus/sta.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
old_rtl/quartus/syn.chg
Normal file
1
old_rtl/quartus/syn.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
40
old_rtl/quartus/vortex.ini
Normal file
40
old_rtl/quartus/vortex.ini
Normal file
@@ -0,0 +1,40 @@
|
||||
load_package flow
|
||||
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
|
||||
set_global_assignment -name SDC_FILE vortex.sdc
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
# pins configuration
|
||||
package require cmdline
|
||||
|
||||
proc make_all_pins_virtual { args } {
|
||||
|
||||
set options {\
|
||||
{ "exclude.arg" "" "List of signals to exclude" } \
|
||||
}
|
||||
array set opts [::cmdline::getoptions quartus(args) $options]
|
||||
|
||||
remove_all_instance_assignments -name VIRTUAL_PIN
|
||||
execute_module -tool map
|
||||
set name_ids [get_names -filter * -node_type pin]
|
||||
|
||||
foreach_in_collection name_id $name_ids {
|
||||
set pin_name [get_name_info -info full_path $name_id]
|
||||
|
||||
if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
|
||||
post_message "Making VIRTUAL_PIN assignment to $pin_name"
|
||||
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
|
||||
} else {
|
||||
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
|
||||
}
|
||||
}
|
||||
export_assignments
|
||||
}
|
||||
|
||||
|
||||
make_all_pins_virtual -exclude { clk, reset }
|
||||
1
old_rtl/quartus/vortex.sdc
Normal file
1
old_rtl/quartus/vortex.sdc
Normal file
@@ -0,0 +1 @@
|
||||
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||
Reference in New Issue
Block a user