From 59cc0d5be9c93d988d48157579cf29bf90b86fda Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 6 May 2020 13:33:16 -0400 Subject: [PATCH] rtl multicore fix --- hw/Makefile | 3 ++- hw/rtl/cache/VX_bank.v | 9 ++++----- hw/rtl/cache/VX_tag_data_access.v | 5 ++--- hw/simulate/simulator.cpp | 14 ++++++-------- hw/simulate/simulator.h | 2 +- 5 files changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/Makefile b/hw/Makefile index 9560392a..f3c9f2ca 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -6,7 +6,8 @@ VF += --language 1800-2009 --assert -Wall -Wpedantic VF += -exe $(SRCS) $(INCLUDE) -MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 +#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index f03b7874..d6e646f5 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -509,15 +509,15 @@ module VX_bank #( // TODO: should investigae the need for "SNOOP_FORWARDING" here wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full - && !(SNOOP_FORWARDING && (miss_add_mem_write == `BYTE_EN_NO)) + && (miss_add_mem_write == `BYTE_EN_NO) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full)); - wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2; - wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid; - wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag; + wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2; + wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid; + wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag; wire cwbq_empty; assign core_rsp_valid = !cwbq_empty; @@ -589,7 +589,6 @@ module VX_bank #( .possible_fill (possible_fill), .success_fill (is_fill_st2), .fill_addr (fill_invalidator_addr), - .invalidate_fill (invalidate_fill) ); diff --git a/hw/rtl/cache/VX_tag_data_access.v b/hw/rtl/cache/VX_tag_data_access.v index 22a804c2..d76a7be8 100644 --- a/hw/rtl/cache/VX_tag_data_access.v +++ b/hw/rtl/cache/VX_tag_data_access.v @@ -263,12 +263,11 @@ module VX_tag_data_access #( wire[`TAG_SELECT_BITS-1:0] writeaddr_tag = writeaddr_st1e[`TAG_LINE_ADDR_RNG]; - wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; - wire tags_match = writeaddr_tag == use_read_tag_st1e; + wire tags_match = writeaddr_tag == use_read_tag_st1e; wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e; wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; - wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch; + wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match; assign miss_st1e = snoop_hit || req_invalid || req_miss; assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index ea4f68e8..041a4d15 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -158,17 +158,15 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { // submit snoop requests for the needed blocks vortex_->snp_req_addr = aligned_addr_start; - vortex_->snp_req_valid = false; + vortex_->snp_req_valid = true; for (;;) { this->step(); - if (vortex_->snp_req_valid) { - vortex_->snp_req_valid = false; - if (vortex_->snp_req_addr >= aligned_addr_end) - break; + if (vortex_->snp_req_valid && vortex_->snp_req_ready) { vortex_->snp_req_addr += 1; - } - if (vortex_->snp_req_ready) { - vortex_->snp_req_valid = true; + if (vortex_->snp_req_addr >= aligned_addr_end) { + vortex_->snp_req_valid = false; + break; + } } } this->wait(PIPELINE_FLUSH_LATENCY); diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 209ebc0b..b6ee4d08 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -18,7 +18,7 @@ #define DRAM_LATENCY 100 #define DRAM_RQ_SIZE 16 #define DRAM_STALLS_MODULO 16 -#define PIPELINE_FLUSH_LATENCY 300 +#define PIPELINE_FLUSH_LATENCY 1000 typedef struct { int cycles_left;