scope fixes ...
This commit is contained in:
@@ -44,10 +44,10 @@
|
||||
|
||||
static constexpr int num_modules = sizeof(scope_modules) / sizeof(scope_module_t);
|
||||
|
||||
static constexpr int num_signals = sizeof(scope_taps) / sizeof(scope_tap_t);
|
||||
static constexpr int num_taps = sizeof(scope_taps) / sizeof(scope_tap_t);
|
||||
|
||||
constexpr int calcFrameWidth(int index = 0) {
|
||||
return (index < num_signals) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0;
|
||||
return (index < num_taps) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0;
|
||||
}
|
||||
|
||||
static constexpr int fwidth = calcFrameWidth();
|
||||
@@ -77,13 +77,12 @@ uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) {
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
void dump_taps(std::ofstream& ofs, int module) {
|
||||
int i = 1;
|
||||
for (auto& tap : scope_taps) {
|
||||
void dump_taps(std::ofstream& ofs, int module) {
|
||||
for (int i = 0; i < num_taps; ++i) {
|
||||
auto& tap = scope_taps[i];
|
||||
if (tap.module != module)
|
||||
continue;
|
||||
ofs << "$var reg " << tap.width << " " << i << " " << tap.name << " $end" << std::endl;
|
||||
i += 1;
|
||||
ofs << "$var reg " << tap.width << " " << (i + 1) << " " << tap.name << " $end" << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -91,10 +90,16 @@ void dump_module(std::ofstream& ofs, int parent) {
|
||||
for (auto& module : scope_modules) {
|
||||
if (module.parent != parent)
|
||||
continue;
|
||||
ofs << "$scope module " << module.name << " $end" << std::endl;
|
||||
if (module.name[0] == '*') {
|
||||
ofs << "$var reg 1 0 clk $end" << std::endl;
|
||||
} else {
|
||||
ofs << "$scope module " << module.name << " $end" << std::endl;
|
||||
}
|
||||
dump_module(ofs, module.index);
|
||||
dump_taps(ofs, module.index);
|
||||
ofs << "$upscope $end" << std::endl;
|
||||
if (module.name[0] != '*') {
|
||||
ofs << "$upscope $end" << std::endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -138,7 +143,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
|
||||
ofs << "$version Generated by Vortex Scope $end" << std::endl;
|
||||
ofs << "$timescale 1 ns $end" << std::endl;
|
||||
ofs << "$scope module TOP $end" << std::endl;
|
||||
ofs << "$var reg 1 0 clk $end" << std::endl;
|
||||
|
||||
dump_module(ofs, -1);
|
||||
dump_taps(ofs, -1);
|
||||
ofs << "$upscope $end" << std::endl;
|
||||
@@ -187,7 +192,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
|
||||
// print clock header
|
||||
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
|
||||
timestamp = print_clock(ofs, offset + delta + 2, timestamp);
|
||||
signal_id = num_signals;
|
||||
signal_id = num_taps;
|
||||
|
||||
std::vector<char> signal_data(frame_width+1);
|
||||
|
||||
@@ -229,7 +234,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
|
||||
// print clock header
|
||||
CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta));
|
||||
timestamp = print_clock(ofs, delta + 1, timestamp);
|
||||
signal_id = num_signals;
|
||||
signal_id = num_taps;
|
||||
if (0 == (frame_no % 100)) {
|
||||
std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user