merge update

2021-10-15 19:58:13 -07:00
parent e380ded5e1
commit 58a2140b92
31 changed files with 169 additions and 98 deletions
--- a/hw/rtl/tex_unit/VX_tex_addr.sv
+++ b/hw/rtl/tex_unit/VX_tex_addr.sv
--- a/hw/rtl/tex_unit/VX_tex_format.sv
+++ b/hw/rtl/tex_unit/VX_tex_format.sv
--- a/hw/rtl/tex_unit/VX_tex_lerp.sv
+++ b/hw/rtl/tex_unit/VX_tex_lerp.sv
--- a/hw/rtl/tex_unit/VX_tex_memory.sv
+++ b/hw/rtl/tex_unit/VX_tex_memory.sv
@@ -70,9 +70,9 @@ module VX_tex_memory #(
    assign reqq_push = req_valid && req_ready;
    
    VX_fifo_queue #(
-        .DATAW      ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFOW + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * NUM_REQS * 2) + 4), 
-        .SIZE       (`LSUQ_SIZE),
-        .OUTPUT_REG (1)
+        .DATAW   ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFOW + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * NUM_REQS * 2) + 4), 
+        .SIZE    (`LSUQ_SIZE),
+        .OUT_REG (1)
    ) req_queue (
        .clk        (clk),
        .reset      (reset),
--- a/hw/rtl/tex_unit/VX_tex_sampler.sv
+++ b/hw/rtl/tex_unit/VX_tex_sampler.sv
--- a/hw/rtl/tex_unit/VX_tex_sat.sv
+++ b/hw/rtl/tex_unit/VX_tex_sat.sv
--- a/hw/rtl/tex_unit/VX_tex_stride.sv
+++ b/hw/rtl/tex_unit/VX_tex_stride.sv
--- a/hw/rtl/tex_unit/VX_tex_unit.sv
+++ b/hw/rtl/tex_unit/VX_tex_unit.sv
@@ -7,15 +7,15 @@ module VX_tex_unit #(
    input wire  reset,    

    // Texture unit <-> Memory Unit
-    VX_dcache_req_if dcache_req_if,
-    VX_dcache_rsp_if dcache_rsp_if,
+    VX_dcache_req_if.master dcache_req_if,
+    VX_dcache_rsp_if.slave  dcache_rsp_if,

    // Inputs
-    VX_tex_req_if   tex_req_if,
-    VX_tex_csr_if   tex_csr_if,
+    VX_tex_req_if.slave     tex_req_if,
+    VX_tex_csr_if.slave     tex_csr_if,

    // Outputs
-    VX_tex_rsp_if   tex_rsp_if
+    VX_tex_rsp_if.master    tex_rsp_if
 );

    localparam REQ_INFOW_S = `NR_BITS + 1 + `NW_BITS + 32;
--- a/hw/rtl/tex_unit/VX_tex_wrap.sv
+++ b/hw/rtl/tex_unit/VX_tex_wrap.sv