merge update

2021-10-15 19:58:13 -07:00
parent e380ded5e1
commit 58a2140b92
31 changed files with 169 additions and 98 deletions
--- a/hw/rtl/interfaces/VX_tex_rsp_if.sv
+++ b/hw/rtl/interfaces/VX_tex_rsp_if.sv
@@ -14,6 +14,28 @@ interface VX_tex_rsp_if ();
    wire [`NUM_THREADS-1:0][31:0] data;
    wire                    ready;

+    modport master (
+        output valid,
+        output wid,
+        output tmask,
+        output PC,
+        output rd,
+        output wb,
+        output data,
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  wid,
+        input  tmask,
+        input  PC,
+        input  rd,
+        input  wb,
+        input  data,
+        output ready
+    );
+
 endinterface

 `endif