merge update

hw/rtl/interfaces/VX_gpu_req_if.sv

@@ -12,9 +12,11 @@ interface VX_gpu_req_if();
     wire [31:0]             PC;
     wire [31:0]             next_PC;
     wire [`INST_GPU_BITS-1:0] op_type;
+    wire [`INST_MOD_BITS-1:0] op_mod;
     wire [`NT_BITS-1:0]     tid;
     wire [`NUM_THREADS-1:0][31:0] rs1_data;
-    wire [31:0]             rs2_data;
+    wire [`NUM_THREADS-1:0][31:0] rs2_data;
+    wire [`NUM_THREADS-1:0][31:0] rs3_data;
     wire [`NR_BITS-1:0]     rd;
     wire                    wb;
     
@@ -27,9 +29,11 @@ interface VX_gpu_req_if();
         output PC,
         output next_PC,
         output op_type,
+        output op_mod,
         output tid,
         output rs1_data,
         output rs2_data,
+        output rs3_data,
         output rd,
         output wb,    
         input  ready
@@ -42,9 +46,11 @@ interface VX_gpu_req_if();
         input  PC,
         input  next_PC,
         input  op_type,
+        input  op_mod,
         input  tid,
         input  rs1_data,
         input  rs2_data,
+        input  rs3_data,
         input  rd,
         input  wb,    
         output ready

hw/rtl/interfaces/VX_tex_csr_if.sv

@@ -7,7 +7,19 @@ interface VX_tex_csr_if ();
 
     wire                      write_enable; 
     wire [`CSR_ADDR_BITS-1:0] write_addr;
-    wire [31:0]               write_data;   
+    wire [31:0]               write_data;  
+
+    modport master (
+        output write_enable,
+        output write_addr,
+        output write_data
+    );
+
+    modport slave (
+        input write_enable,
+        input write_addr,
+        input write_data
+    );
 
 endinterface
 

hw/rtl/interfaces/VX_tex_req_if.sv

@@ -18,6 +18,32 @@ interface VX_tex_req_if ();
     
     wire                            ready;
 
+    modport master (
+        output valid,
+        output wid,
+        output tmask,
+        output PC,
+        output rd,
+        output wb,
+        output unit,
+        output coords,
+        output lod,
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  wid,
+        input  tmask,
+        input  PC,
+        input  rd,
+        input  wb,
+        input  unit,
+        input  coords,
+        input  lod,
+        output ready
+    );
+
 endinterface
 `endif
 

hw/rtl/interfaces/VX_tex_rsp_if.sv

@@ -14,6 +14,28 @@ interface VX_tex_rsp_if ();
     wire [`NUM_THREADS-1:0][31:0] data;
     wire                    ready;
 
+    modport master (
+        output valid,
+        output wid,
+        output tmask,
+        output PC,
+        output rd,
+        output wb,
+        output data,
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  wid,
+        input  tmask,
+        input  PC,
+        input  rd,
+        input  wb,
+        input  data,
+        output ready
+    );
+
 endinterface
 
 `endif