RTL code refactoring

2020-04-20 06:59:13 -04:00
parent 07135263f5
commit 58850a2fe8
6 changed files with 22 additions and 23 deletions
--- a/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
+++ b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
@@ -15,11 +15,10 @@ interface VX_gpu_dcache_rsp_if #(
 `IGNORE_WARNINGS_END    
    wire [NUM_REQUESTS-1:0][31:0]  core_wb_pc;    
    wire [NUM_REQUESTS-1:0][31:0]  core_wb_readdata;
+    wire                           core_no_wb_slot;
    
    // Core response meta data
-    wire [`NW_BITS-1:0]            core_wb_warp_num;  
-
-    wire                           core_req_ready;
+    wire [`NW_BITS-1:0]            core_wb_warp_num;      

 endinterface