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RTL refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 07:13:56 -07:00
parent b6ce2dd3b8
commit 5798cf6e15
7 changed files with 39 additions and 32 deletions
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7
hw/opae/README
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@@ -37,3 +37,10 @@ cd /driver/tests/basic
make clean make clean
make make
./basic ./basic
ASE build instructions
vcd file vortex.vcd
vcd add -r /*/Vortex/hw/rtl/*
run -all

2
hw/opae/sources.txt
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@@ -70,7 +70,7 @@ vortex_afu.json
../rtl/VX_gpr.v ../rtl/VX_gpr.v
../rtl/VX_gpr_stage.v ../rtl/VX_gpr_stage.v
../rtl/VX_dmem_ctrl.v ../rtl/VX_dmem_ctrl.v
../rtl/VX_alu.v ../rtl/VX_alu_unit.v
../rtl/VX_csr_data.v ../rtl/VX_csr_data.v
../rtl/VX_lsu.v ../rtl/VX_lsu.v
../rtl/VX_decode.v ../rtl/VX_decode.v

2
hw/rtl/VX_alu.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_alu ( module VX_alu_unit (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire[31:0] src_a, input wire[31:0] src_a,

4
hw/rtl/VX_back_end.v
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@@ -70,7 +70,7 @@ VX_gpr_stage gpr_stage (
.gpr_stage_delay (gpr_stage_delay) .gpr_stage_delay (gpr_stage_delay)
); );
VX_lsu load_store_unit ( VX_lsu_unit lsu_unit (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.lsu_req_if (lsu_req_if), .lsu_req_if (lsu_req_if),
@@ -109,7 +109,7 @@ VX_csr_pipe #(
.stall_gpr_csr(stall_gpr_csr) .stall_gpr_csr(stall_gpr_csr)
); );
VX_writeback wb ( VX_writeback writeback (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.mem_wb_if (mem_wb_if), .mem_wb_if (mem_wb_if),

4
hw/rtl/VX_front_end.v
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@@ -62,8 +62,8 @@ module VX_front_end (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.freeze (freeze_fi_reg), .freeze (freeze_fi_reg),
.fe_inst_meta_fd(fe_inst_meta_fi), .fe_inst_meta_fd (fe_inst_meta_fi),
.fd_inst_meta_de(fe_inst_meta_fi2) .fd_inst_meta_de (fe_inst_meta_fi2)
); );
VX_icache_stage icache_stage( VX_icache_stage icache_stage(

0
hw/rtl/VX_lsu.v → hw/rtl/VX_lsu_unit.v
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4
hw/rtl/Vortex.v
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@@ -159,7 +159,7 @@ VX_front_end front_end (
.fetch_ebreak (ebreak) .fetch_ebreak (ebreak)
); );
VX_scheduler schedule ( VX_scheduler scheduler (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.memory_delay (memory_delay), .memory_delay (memory_delay),
@@ -189,7 +189,7 @@ VX_back_end #(
.gpr_stage_delay (gpr_stage_delay) .gpr_stage_delay (gpr_stage_delay)
); );
VX_dmem_ctrl dmem_controller ( VX_dmem_ctrl dmem_ctrl (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),