decode op_mod optimization
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@@ -10,7 +10,8 @@ interface VX_alu_req_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`ALU_BR_BITS-1:0] op;
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wire [`ALU_BR_BITS-1:0] op_type;
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wire is_br_op;
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wire rs1_is_PC;
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wire rs2_is_imm;
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wire [31:0] imm;
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@@ -10,7 +10,7 @@ interface VX_csr_req_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`CSR_BITS-1:0] op;
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wire [`CSR_BITS-1:0] op_type;
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wire [`CSR_ADDR_BITS-1:0] csr_addr;
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wire [31:0] csr_mask;
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wire [`NR_BITS-1:0] rd;
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@@ -12,8 +12,8 @@ interface VX_decode_if ();
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wire [31:0] curr_PC;
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wire [`EX_BITS-1:0] ex_type;
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wire [`OP_BITS-1:0] ex_op;
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wire [`FRM_BITS-1:0] frm;
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wire [`OP_BITS-1:0] op_type;
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wire [`MOD_BITS-1:0] op_mod;
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wire wb;
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wire [`NR_BITS-1:0] rd;
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@@ -14,7 +14,7 @@ interface VX_fpu_req_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`FPU_BITS-1:0] op;
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wire [`FPU_BITS-1:0] op_type;
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wire [`FRM_BITS-1:0] frm;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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@@ -10,7 +10,7 @@ interface VX_gpu_req_if();
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`GPU_BITS-1:0] op;
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wire [`GPU_BITS-1:0] op_type;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [31:0] rs2_data;
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wire [`NR_BITS-1:0] rd;
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@@ -13,7 +13,7 @@ interface VX_issue_if ();
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wire [31:0] curr_PC;
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wire [`EX_BITS-1:0] ex_type;
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wire [`OP_BITS-1:0] ex_op;
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wire [`OP_BITS-1:0] op_type;
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wire [`FRM_BITS-1:0] frm;
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@@ -14,7 +14,7 @@ interface VX_mul_req_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] thread_mask;
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wire [31:0] curr_PC;
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wire [`MUL_BITS-1:0] op;
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wire [`MUL_BITS-1:0] op_type;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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wire [`NR_BITS-1:0] rd;
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