pipeline refactoring

hw/rtl/interfaces/VX_branch_ctl_if.v

@@ -0,0 +1,15 @@
+`ifndef VX_BRANCH_RSP_IF
+`define VX_BRANCH_RSP_IF
+
+`include "VX_define.vh"
+
+interface VX_branch_ctl_if ();
+
+    wire                valid;    
+    wire [`NW_BITS-1:0] warp_num;    
+    wire                taken;
+    wire [31:0]         dest;
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_commit_if.v

@@ -0,0 +1,19 @@
+`ifndef VX_COMMIT_IF
+`define VX_COMMIT_IF
+
+`include "VX_define.vh"
+
+interface VX_commit_if ();
+
+    wire [`NUM_THREADS-1:0]         valid;
+    wire [`NW_BITS-1:0]             warp_num;
+    wire [31:0]                     curr_PC;  
+    wire [`NUM_THREADS-1:0][31:0]	data; 
+    wire [`NR_BITS-1:0]             rd;
+    wire [`WB_BITS-1:0]             wb;        
+    wire                            is_io;
+    wire                            ready;
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_execute_if.v

@@ -3,7 +3,7 @@
 
 `include "VX_define.vh"
 
-interface VX_execute_if();
+interface VX_execute_if ();
 
     wire [`NUM_THREADS-1:0] valid;
     wire [`NW_BITS-1:0]     warp_num;

hw/rtl/interfaces/VX_gpu_req_if.v

@@ -7,12 +7,13 @@ interface VX_gpu_req_if();
 
     wire [`NUM_THREADS-1:0]  valid;
     wire [`NW_BITS-1:0]      warp_num;
-    wire [31:0]              next_PC;
+    wire [31:0]              curr_PC;
 
     wire [`GPU_BITS-1:0]     gpu_op;
 
     wire [`NUM_THREADS-1:0][31:0] rs1_data;
     wire [31:0]              rs2_data;
+    wire [31:0]              next_PC;
     
     wire                     ready;
 

hw/rtl/interfaces/VX_perf_cntrs_if.v

@@ -0,0 +1,13 @@
+`ifndef VX_PERF_CNTRS_IF
+`define VX_PERF_CNTRS_IF
+
+`include "VX_define.vh"
+
+interface VX_perf_cntrs_if ();
+
+    wire [63:0] total_cycles;
+    wire [63:0] total_instrs;
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_wb_if.v

@@ -6,12 +6,9 @@
 interface VX_wb_if ();
 
     wire [`NUM_THREADS-1:0]         valid;
-    wire [`NW_BITS-1:0]             warp_num;
-    wire [31:0]                     curr_PC;  
+    wire [`NW_BITS-1:0]             warp_num; 
     wire [`NUM_THREADS-1:0][31:0]	data; 
     wire [`NR_BITS-1:0]             rd;
-    wire [`WB_BITS-1:0]             wb;        
-    wire                            is_io;
     wire                            ready;
 
 endinterface