pipeline refactoring
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2
hw/rtl/cache/VX_cache_core_rsp_merge.v
vendored
2
hw/rtl/cache/VX_cache_core_rsp_merge.v
vendored
@@ -46,7 +46,7 @@ module VX_cache_core_rsp_merge #(
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reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
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reg [NUM_BANKS-1:0] core_rsp_bank_select;
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wire stall = ~core_rsp_ready;
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wire stall = ~core_rsp_ready && (| core_rsp_valid);
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integer i;
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