generic_register reset network optimization

2020-11-29 18:41:36 -08:00
parent def6a35693
commit 5758ef9ebf
21 changed files with 84 additions and 48 deletions
--- a/hw/rtl/cache/VX_cache_dram_req_arb.v
+++ b/hw/rtl/cache/VX_cache_dram_req_arb.v
@@ -48,6 +48,7 @@ module VX_cache_dram_req_arb #(

        VX_generic_register #(
            .N(1 + `DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
+            .R(1),
            .PASSTHRU(NUM_BANKS <= 2)
        ) pipe_reg (
            .clk   (clk),