synthesis optimizations

hw/rtl/VX_scoreboard.v

@@ -11,11 +11,17 @@ module VX_scoreboard  #(
     output wire     delay
 );
     reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs;
-    wire [`NUM_REGS-1:0] deq_inuse_regs;
-    
-    assign deq_inuse_regs = inuse_regs[ibuf_deq_if.wid] & ibuf_deq_if.used_regs;
 
-    assign delay = (| deq_inuse_regs);
+    reg is_reg_busy;
+    always @(*) begin
+        is_reg_busy = 0;
+        for (integer i = 0; i < `NUM_WARPS; ++i) begin
+            if (ibuf_deq_if.wid == `NW_BITS'(i)) begin
+                is_reg_busy = | (inuse_regs[i] & ibuf_deq_if.used_regs);
+            end
+        end
+    end
+    assign delay = is_reg_busy;
     
     wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && (ibuf_deq_if.wb != 0);
 
@@ -37,6 +43,8 @@ module VX_scoreboard  #(
         end    
     end
 
+    wire [`NUM_REGS-1:0] deq_inuse_regs = inuse_regs[ibuf_deq_if.wid];
+
 `ifdef DBG_PRINT_PIPELINE
     always @(posedge clk) begin
         if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin