Fully-functioning spawn and join instructions.
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@@ -121,12 +121,16 @@ void Instruction::executeOn(Core &c) {
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return;
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}
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/* Also throw exceptions on divergent branches. */
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if (predicated && instTable[op].controlFlow) {
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bool p0 = c.pred[0][pred];
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for (Size t = 1; t < c.activeThreads; t++) {
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if (c.pred[t][pred] != p0) throw DivergentBranchException();
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/* Also throw exceptions on non-masked divergent branches. */
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if (instTable[op].controlFlow) {
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Size t, count, active;
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for (t = 0, count = 0, active = 0; t < c.activeThreads; ++t) {
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if ((!predicated || c.pred[t][pred]) && c.tmask[t]) ++count;
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if (c.tmask[t]) ++active;
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}
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if (count != 0 && count != active)
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throw DivergentBranchException();
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}
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Size nextActiveThreads = c.activeThreads;
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@@ -135,8 +139,12 @@ void Instruction::executeOn(Core &c) {
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for (Size t = 0; t < c.activeThreads; t++) {
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vector<Reg<Word> > ®(c.reg[t]);
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vector<Reg<bool> > &pReg(c.pred[t]);
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stack<DomStackEntry> &domStack(c.domStack);
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if (predicated && !pReg[pred]) continue;
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// If this thread is masked out, don't execute the instruction, unless it's
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// a split or join.
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if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
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op != SPLIT && op != JOIN) continue;
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Word memAddr;
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switch (op) {
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@@ -282,6 +290,23 @@ void Instruction::executeOn(Core &c) {
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case FDIV: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) /
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double(Float(reg[rsrc[1]], wordSz)),wordSz);
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break;
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case SPLIT:if (t == 0) {
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// TODO: if mask becomes all-zero, fall through
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DomStackEntry e(pred, c.pred, c.pc);
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c.domStack.push(c.tmask);
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c.domStack.push(e);
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for (unsigned i = 0; i < e.tmask.size(); ++i)
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c.tmask[i] = !e.tmask[i];
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}
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break;
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case JOIN: if (t == 0) {
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// TODO: if mask becomes all-zero, fall through
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if (!c.domStack.top().fallThrough)
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c.pc = c.domStack.top().pc;
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c.tmask = c.domStack.top().tmask;
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c.domStack.pop();
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}
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break;
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default:
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cout << "ERROR: Unsupported instruction: " << *this << "\n";
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exit(1);
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