From 559c64cb36690f55d4237df44014ca889b063f79 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 18 Oct 2019 02:20:38 -0400 Subject: [PATCH] Cleanup --- rtl/VX_back_end.v | 9 ++------- rtl/VX_decode.v | 9 ++++----- rtl/VX_execute_unit.v | 6 +----- rtl/VX_fetch.v | 26 ++++++++++---------------- rtl/VX_front_end.v | 24 ++++++++++-------------- rtl/VX_gpr_stage.v | 12 +++++------- rtl/VX_gpr_wrapper.v | 8 ++------ rtl/Vortex.v | 10 ++-------- rtl/interfaces/VX_wstall_inter.v | 15 +++++++++++++++ rtl/pipe_regs/VX_d_e_reg.v | 3 +-- rtl/pipe_regs/VX_f_d_reg.v | 3 +-- syn/syn.tcl | 2 +- 12 files changed, 54 insertions(+), 73 deletions(-) create mode 100644 rtl/interfaces/VX_wstall_inter.v diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index b0a64d33..2830b1a7 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -5,10 +5,7 @@ module VX_back_end ( input wire schedule_delay, input wire[31:0] csr_decode_csr_data, - output wire execute_branch_stall, - output wire out_mem_delay, - output wire out_gpr_stall, VX_jal_response_inter VX_jal_rsp, VX_branch_response_inter VX_branch_rsp, @@ -69,8 +66,7 @@ VX_gpr_stage VX_gpr_stage( .VX_bckE_req (VX_bckE_req), .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req_out (VX_bckE_req_out), - .VX_gpr_data (VX_gpr_data), - .out_gpr_stall (out_gpr_stall) + .VX_gpr_data (VX_gpr_data) ); @@ -102,8 +98,7 @@ VX_execute_unit VX_execUnit( .in_csr_data (csr_decode_csr_data), .out_csr_address (VX_csr_w_req.csr_address), .out_is_csr (VX_csr_w_req.is_csr), - .out_csr_result (VX_csr_w_req.csr_result), - .out_branch_stall(execute_branch_stall) + .out_csr_result (VX_csr_w_req.csr_result) ); VX_writeback VX_wb( diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 01a717a0..69497ff1 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -7,14 +7,11 @@ module VX_decode( // Outputs VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, - output reg out_gpr_stall, - output reg out_branch_stall, + VX_wstall_inter VX_wstall, output wire out_ebreak ); - assign out_gpr_stall = 0; - wire[31:0] in_instruction = fd_inst_meta_de.instruction; wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; wire[`NW_M1:0] in_warp_num = fd_inst_meta_de.warp_num; @@ -313,7 +310,9 @@ module VX_decode( end assign VX_frE_to_bckE_req.branch_type = temp_branch_type; - assign out_branch_stall = temp_branch_stall && in_valid[0]; + + assign VX_wstall.wstall = temp_branch_stall && in_valid[0]; + assign VX_wstall.warp_num = in_warp_num; always @(*) begin // ALU OP diff --git a/rtl/VX_execute_unit.v b/rtl/VX_execute_unit.v index e4ac5bf2..20172229 100644 --- a/rtl/VX_execute_unit.v +++ b/rtl/VX_execute_unit.v @@ -15,10 +15,7 @@ module VX_execute_unit ( input wire[31:0] in_csr_data, output wire[11:0] out_csr_address, output wire out_is_csr, - output reg[31:0] out_csr_result, - output wire out_branch_stall - - + output reg[31:0] out_csr_result ); @@ -111,7 +108,6 @@ module VX_execute_unit ( assign VX_branch_rsp.branch_dir = temp_branch_dir; assign VX_branch_rsp.branch_warp_num = VX_exec_unit_req.warp_num; assign VX_branch_rsp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset - assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL; always @(*) begin diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 676edd94..e142cd10 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -2,17 +2,15 @@ `include "VX_define.v" module VX_fetch ( - input wire clk, - input wire in_memory_delay, - input wire in_branch_stall, - input wire in_branch_stall_exe, - input wire in_gpr_stall, - input wire schedule_delay, + input wire clk, + input wire in_memory_delay, + VX_wstall_inter VX_wstall, + input wire schedule_delay, VX_icache_response_inter icache_response, - VX_icache_request_inter icache_request, + VX_icache_request_inter icache_request, - output wire out_delay, - output wire out_ebreak, + output wire out_delay, + output wire out_ebreak, VX_jal_response_inter VX_jal_rsp, VX_branch_response_inter VX_branch_rsp, VX_inst_meta_inter fe_inst_meta_fd, @@ -25,12 +23,9 @@ module VX_fetch ( // Locals wire pipe_stall; - wire warp_stall; - assign pipe_stall = in_gpr_stall || in_freeze || schedule_delay; - - assign warp_stall = in_branch_stall || (in_branch_stall_exe && 0); + assign pipe_stall = in_freeze || schedule_delay; wire[`NT_M1:0] thread_mask; wire[`NW_M1:0] warp_num; @@ -49,8 +44,8 @@ module VX_fetch ( .whalt (VX_warp_ctl.ebreak), .whalt_warp_num (VX_warp_ctl.warp_num), // Wstall - .wstall (warp_stall), - .wstall_warp_num(VX_warp_ctl.warp_num), + .wstall (VX_wstall.wstall), + .wstall_warp_num(VX_wstall.warp_num), // JAL .jal (VX_jal_rsp.jal), @@ -77,7 +72,6 @@ module VX_fetch ( assign fe_inst_meta_fd.warp_num = warp_num; assign fe_inst_meta_fd.valid = thread_mask; - // assign fe_inst_meta_fd.instruction = (pipe_stall || warp_stall) ? 32'b0 : icache_response.instruction;; assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction;; assign fe_inst_meta_fd.inst_pc = warp_pc; diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index 01aa9e81..d972a747 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -4,10 +4,7 @@ module VX_front_end ( input wire clk, input wire reset, - input wire memory_delay, - - input wire execute_branch_stall, - input wire in_gpr_stall, + input wire memory_delay, input wire schedule_delay, VX_warp_ctl_inter VX_warp_ctl, @@ -34,22 +31,22 @@ VX_inst_meta_inter fd_inst_meta_de(); // From decode wire decode_branch_stall; -wire decode_gpr_stall; -wire total_freeze = memory_delay || fetch_delay || in_gpr_stall || schedule_delay; +wire total_freeze = memory_delay || fetch_delay || schedule_delay; /* verilator lint_off UNUSED */ wire real_fetch_ebreak; /* verilator lint_on UNUSED */ + +VX_wstall_inter VX_wstall(); + VX_fetch vx_fetch( .clk (clk), + .VX_wstall (VX_wstall), .in_memory_delay (memory_delay), - .in_branch_stall (decode_branch_stall), .schedule_delay (schedule_delay), - .in_branch_stall_exe(execute_branch_stall), - .in_gpr_stall (decode_gpr_stall), .VX_jal_rsp (VX_jal_rsp), .icache_response (icache_response_fe), .VX_warp_ctl (VX_warp_ctl), @@ -65,7 +62,6 @@ VX_f_d_reg vx_f_d_reg( .clk (clk), .reset (reset), .in_freeze (total_freeze), - .in_gpr_stall (decode_gpr_stall), .fe_inst_meta_fd(fe_inst_meta_fd), .fd_inst_meta_de(fd_inst_meta_de) ); @@ -74,17 +70,17 @@ VX_f_d_reg vx_f_d_reg( VX_decode vx_decode( .fd_inst_meta_de (fd_inst_meta_de), .VX_frE_to_bckE_req(VX_frE_to_bckE_req), - .out_gpr_stall (decode_gpr_stall), - .out_branch_stall (decode_branch_stall), + .VX_wstall (VX_wstall), .out_ebreak (fetch_ebreak) ); +wire no_br_stall = 0; + VX_d_e_reg vx_d_e_reg( .clk (clk), .reset (reset), - .in_branch_stall(execute_branch_stall), + .in_branch_stall(no_br_stall), .in_freeze (total_freeze), - .in_gpr_stall (decode_gpr_stall), .VX_frE_to_bckE_req(VX_frE_to_bckE_req), .VX_bckE_req (VX_bckE_req) ); diff --git a/rtl/VX_gpr_stage.v b/rtl/VX_gpr_stage.v index 43fbe717..eef624b4 100644 --- a/rtl/VX_gpr_stage.v +++ b/rtl/VX_gpr_stage.v @@ -16,9 +16,7 @@ module VX_gpr_stage ( // Original Request 1 cycle later VX_frE_to_bckE_req_inter VX_bckE_req_out, // Data Read - VX_gpr_data_inter VX_gpr_data, - - output wire out_gpr_stall + VX_gpr_data_inter VX_gpr_data ); @@ -47,8 +45,7 @@ module VX_gpr_stage ( .VX_gpr_jal (VX_gpr_jal), .out_a_reg_data (VX_gpr_datf.a_reg_data), - .out_b_reg_data (VX_gpr_datf.b_reg_data), - .out_gpr_stall(out_gpr_stall) + .out_b_reg_data (VX_gpr_datf.b_reg_data) ); // assign VX_bckE_req.is_csr = is_csr; @@ -66,13 +63,14 @@ module VX_gpr_stage ( .out ({VX_gpr_data.a_reg_data, VX_gpr_data.b_reg_data}) ); + wire stall = schedule_delay; + VX_d_e_reg gpr_stage_reg( .clk (clk), .reset (zero_temp), - .in_branch_stall (schedule_delay), + .in_branch_stall (stall), .in_freeze (zero_temp), - .in_gpr_stall (out_gpr_stall), .VX_frE_to_bckE_req(VX_bckE_req), .VX_bckE_req (VX_bckE_req_out) ); diff --git a/rtl/VX_gpr_wrapper.v b/rtl/VX_gpr_wrapper.v index 47c666c6..93cad91e 100644 --- a/rtl/VX_gpr_wrapper.v +++ b/rtl/VX_gpr_wrapper.v @@ -7,8 +7,7 @@ module VX_gpr_wrapper ( VX_gpr_jal_inter VX_gpr_jal, output wire[`NT_M1:0][31:0] out_a_reg_data, - output wire[`NT_M1:0][31:0] out_b_reg_data, - output wire out_gpr_stall + output wire[`NT_M1:0][31:0] out_b_reg_data ); @@ -40,10 +39,7 @@ module VX_gpr_wrapper ( end - endgenerate - - assign out_gpr_stall = 0; - + endgenerate endmodule diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 63de5349..53288030 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -50,7 +50,6 @@ wire fetch_delay; VX_wb_inter VX_writeback_inter(); // Writeback to GPRs VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch -wire execute_branch_stall; wire memory_delay; // CSR Buses @@ -62,7 +61,6 @@ wire[11:0] decode_csr_address; VX_warp_ctl_inter VX_warp_ctl(); -wire out_gpr_stall; wire schedule_delay; @@ -70,7 +68,6 @@ VX_front_end vx_front_end( .clk (clk), .reset (reset), .VX_warp_ctl (VX_warp_ctl), - .execute_branch_stall(execute_branch_stall), .VX_bckE_req (VX_bckE_req), .decode_csr_address (decode_csr_address), .memory_delay (memory_delay), @@ -80,8 +77,7 @@ VX_front_end vx_front_end( .icache_request_fe (icache_request_fe), .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), - .fetch_ebreak (out_ebreak), - .in_gpr_stall (out_gpr_stall) + .fetch_ebreak (out_ebreak) ); VX_scheduler schedule( @@ -99,15 +95,13 @@ VX_back_end vx_back_end( .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req (VX_bckE_req), .csr_decode_csr_data (csr_decode_csr_data), - .execute_branch_stall(execute_branch_stall), .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), .VX_dcache_rsp (VX_dcache_rsp), .VX_dcache_req (VX_dcache_req), .VX_csr_w_req (VX_csr_w_req), .VX_writeback_inter (VX_writeback_inter), - .out_mem_delay (memory_delay), - .out_gpr_stall (out_gpr_stall) + .out_mem_delay (memory_delay) ); VX_csr_handler vx_csr_handler( diff --git a/rtl/interfaces/VX_wstall_inter.v b/rtl/interfaces/VX_wstall_inter.v new file mode 100644 index 00000000..8699b022 --- /dev/null +++ b/rtl/interfaces/VX_wstall_inter.v @@ -0,0 +1,15 @@ +`include "../VX_define.v" + +`ifndef VX_WSTALL_INTER + +`define VX_WSTALL_INTER + + +interface VX_wstall_inter(); + wire wstall; + wire[`NW_M1:0] warp_num; +endinterface + + + +`endif \ No newline at end of file diff --git a/rtl/pipe_regs/VX_d_e_reg.v b/rtl/pipe_regs/VX_d_e_reg.v index 89f11eee..b5d92649 100644 --- a/rtl/pipe_regs/VX_d_e_reg.v +++ b/rtl/pipe_regs/VX_d_e_reg.v @@ -7,7 +7,6 @@ module VX_d_e_reg ( input wire reset, input wire in_branch_stall, input wire in_freeze, - input wire in_gpr_stall, VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, @@ -16,7 +15,7 @@ module VX_d_e_reg ( wire stall = in_freeze; - wire flush = (in_branch_stall == `STALL) || (in_gpr_stall == `STALL); + wire flush = (in_branch_stall == `STALL); VX_generic_register #(.N(237)) d_e_reg diff --git a/rtl/pipe_regs/VX_f_d_reg.v b/rtl/pipe_regs/VX_f_d_reg.v index 8d802268..62cc8ba4 100644 --- a/rtl/pipe_regs/VX_f_d_reg.v +++ b/rtl/pipe_regs/VX_f_d_reg.v @@ -4,7 +4,6 @@ module VX_f_d_reg ( input wire clk, input wire reset, input wire in_freeze, - input wire in_gpr_stall, VX_inst_meta_inter fe_inst_meta_fd, VX_inst_meta_inter fd_inst_meta_de @@ -12,7 +11,7 @@ module VX_f_d_reg ( ); wire flush = 1'b0; - wire stall = in_freeze == 1'b1 || in_gpr_stall; + wire stall = in_freeze == 1'b1; diff --git a/syn/syn.tcl b/syn/syn.tcl index e6046856..8d432e5a 100755 --- a/syn/syn.tcl +++ b/syn/syn.tcl @@ -3,7 +3,7 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_ set symbol_library {} set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] -set verilog_files [ list VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_csr_write_request_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ +set verilog_files [ list VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_csr_write_request_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ ] analyze -format sverilog $verilog_files