simulation framework refactoring
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123
sim/rtlsim/Makefile
Normal file
123
sim/rtlsim/Makefile
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CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
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#CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
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CXXFLAGS += -fPIC -Wno-maybe-uninitialized
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CXXFLAGS += -I. -I../../../hw -I../../common
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CXXFLAGS += -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
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# control RTL debug print states
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DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
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DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
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DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
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DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
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DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
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DBG_FLAGS += $(DBG_PRINT_FLAGS)
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DBG_FLAGS += -DDBG_CACHE_REQ_INFO
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DBG_FLAGS += -DVCD_OUTPUT
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SINGLECORE = -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0
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MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
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RTL_DIR=../../hw/rtl
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DPI_DIR=../../hw/dpi
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
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SRCS = ../common/util.cpp ../common/mem.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
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SRCS += simulator.cpp
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ifdef AXI_BUS
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TOP = Vortex_axi
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CFLAGS += -DAXI_BUS
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else
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TOP = Vortex
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endif
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VL_FLAGS = --cc $(TOP) --top-module $(TOP)
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VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
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VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += verilator.vlt
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VL_FLAGS += $(CONFIGS)
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VL_FLAGS += $(RTL_INCLUDE)
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)
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CXXFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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CXXFLAGS += -DNDEBUG
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endif
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# Enable perf counters
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ifdef PERF
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VL_FLAGS += -DPERF_ENABLE
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CXXFLAGS += -DPERF_ENABLE
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endif
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# ALU backend
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VL_FLAGS += -DIMUL_DPI
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VL_FLAGS += -DIDIV_DPI
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# FPU backend
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FPU_CORE ?= FPU_FPNEW
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VL_FLAGS += -D$(FPU_CORE)
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THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
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OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS)))
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VPATH := $(sort $(dir $(SRCS)))
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#$(info OBJS is $(OBJS))
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#$(info VPATH is $(VPATH))
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PROJECT = rtlsim
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all: build-s
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build-s:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' -o ../$(PROJECT)
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build-sd:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) $(SINGLECORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT)
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build-st:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS) -o ../$(PROJECT)
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build-m:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' -o ../$(PROJECT)
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build-md:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) $(MULTICORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT)
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build-mt:
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verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS) -o ../$(PROJECT)
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obj_dir/V$(TOP)__ALL.a:
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verilator --build $(VL_FLAGS) -CFLAGS '$(CXXFLAGS)'
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obj_dir/%.o: %.cpp
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cd obj_dir && $(CXX) $(CXXFLAGS) -c ../$< -o $(notdir $@)
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obj_dir/verilated.o: $(VERILATOR_ROOT)/include/verilated.cpp
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cd obj_dir && $(CXX) $(CXXFLAGS) -c $< -o verilated.o
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static: obj_dir/V$(TOP)__ALL.a $(OBJS) obj_dir/verilated.o
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cp obj_dir/V$(TOP)__ALL.a lib$(PROJECT).a
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$(AR) rs lib$(PROJECT).a $(OBJS) obj_dir/verilated.o
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clean-objdir:
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rm -rf obj_dir
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clean: clean-objdir
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rm -rf $(PROJECT) lib$(PROJECT).a
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