LKG build - minor update

.travis.yml

@@ -40,15 +40,18 @@ jobs:
     - stage: test
       name: config
       script: cp -r $PWD ../build4 && cd ../build4 && ./ci/travis_run.py ./ci/regression.sh -config
+    - stage: test
+      name: stress0
+      script: cp -r $PWD ../build5 && cd ../build5 && ./ci/travis_run.py ./ci/regression.sh -stress0
     - stage: test
       name: stress1
-      script: cp -r $PWD ../build5 && cd ../build5 && ./ci/travis_run.py ./ci/regression.sh -stress1
+      script: cp -r $PWD ../build6 && cd ../build6 && ./ci/travis_run.py ./ci/regression.sh -stress1
     - stage: test
       name: stress2
-      script: cp -r $PWD ../build6 && cd ../build6 && ./ci/travis_run.py ./ci/regression.sh -stress2
+      script: cp -r $PWD ../build7 && cd ../build7 && ./ci/travis_run.py ./ci/regression.sh -stress2
     - stage: test
       name: compiler
-      script: cp -r $PWD ../build7 && cd ../build7 && ./ci/travis_run.py /ci/test_compiler.sh
+      script: cp -r $PWD ../build8 && cd ../build8 && ./ci/travis_run.py /ci/test_compiler.sh
   
 after_success:
   # Gather code coverage

ci/regression.sh

@@ -97,32 +97,45 @@ CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=
 # test 128-bit DRAM block
 CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28 -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
 
-# test verilator reset values
-CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
-CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
-
 # test long memory latency
 CONFIGS="-DMEM_LATENCY=100 -DMEM_RQ_SIZE=4 -DMEM_STALLS_MODULO=4" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
 
 echo "configuration tests done!"
 }
 
+stress0() 
+{
+echo "begin stress0 tests..."
+
+# test verilator reset values
+CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm
+CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm
+FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood
+FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood
+CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr
+CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr
+CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf
+CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf
+
+echo "stress0 tests done!"
+}
+
 stress1() 
 {
-echo "begin stress tests..."
+echo "begin stress1 tests..."
 
 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256"
 
-echo "stress tests done!"
+echo "stress1 tests done!"
 }
 
 stress2() 
 {
-echo "begin stress tests..."
+echo "begin stress2 tests..."
 
 ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256"
 
-echo "stress tests done!"
+echo "stress2 tests done!"
 }
 
 usage()
@@ -133,13 +146,15 @@ usage()
 while [ "$1" != "" ]; do
     case $1 in
         -coverage ) coverage
-                    ;;
+                ;;
         -cluster ) cluster
-                     ;;
+                ;;
         -debug ) debug
-                    ;;
+                ;;
         -config ) config
                 ;;
+        -stress0 ) stress0
+                ;;
         -stress1 ) stress1
                 ;;
         -stress2 ) stress2
@@ -148,12 +163,13 @@ while [ "$1" != "" ]; do
                cluster
                debug
                config
+               stress0
                stress1
                stress2
-               ;;
+                ;;
         -h | --help ) usage
                       exit
-                      ;;
+                ;;
         * )           usage
                       exit 1
     esac

hw/rtl/VX_cluster.v

@@ -148,8 +148,8 @@ module VX_cluster #(
 
         VX_mem_arb #(
             .NUM_REQS       (`NUM_CORES),
-            .DATA_WIDTH     (`L2MEM_DATA_WIDTH), 
+            .DATA_WIDTH     (`DMEM_DATA_WIDTH),
-            .ADDR_WIDTH     (`L2MEM_ADDR_WIDTH),           
+            .ADDR_WIDTH     (`DMEM_ADDR_WIDTH),           
             .TAG_IN_WIDTH   (`XMEM_TAG_WIDTH),
             .TAG_SEL_IDX    (1), // Skip 0 for NC flag
             .BUFFERED_REQ   (1),

hw/rtl/VX_define.vh

@@ -247,14 +247,14 @@
 // Cache ID
 `define ICACHE_ID               (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0)
 
-// Block size in bytes
+// Number of banks
-`define ICACHE_LINE_SIZE        `L1_BLOCK_SIZE
+`define INUM_BANKS              1
 
 // Word size in bytes
 `define IWORD_SIZE              4
 
-// Number of banks
+// Block size in bytes
-`define INUM_BANKS              1
+`define ICACHE_LINE_SIZE        `L1_BLOCK_SIZE
 
 // Core request address bits
 `define ICORE_ADDR_WIDTH        (32-`CLOG2(`IWORD_SIZE))
@@ -285,12 +285,12 @@
 // Cache ID
 `define DCACHE_ID               (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1)
 
-// Block size in bytes
-`define DCACHE_LINE_SIZE        `L1_BLOCK_SIZE
-
 // Word size in bytes
 `define DWORD_SIZE              4
 
+// Block size in bytes
+`define DCACHE_LINE_SIZE        `L1_BLOCK_SIZE
+
 // Core request address bits
 `define DCORE_ADDR_WIDTH        (32-`CLOG2(`DWORD_SIZE))
 
@@ -337,12 +337,12 @@
 // Cache ID
 `define L2CACHE_ID              (32'(`L3_ENABLE) + CLUSTER_ID)
 
-// Block size in bytes
-`define L2CACHE_LINE_SIZE       `MEM_BLOCK_SIZE
-
 // Word size in bytes
 `define L2WORD_SIZE             `DCACHE_LINE_SIZE
 
+// Block size in bytes
+`define L2CACHE_LINE_SIZE       (`L2_ENABLE ? `MEM_BLOCK_SIZE : `L2WORD_SIZE)
+
 // Input request tag bits
 `define L2CORE_TAG_WIDTH        (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
 
@@ -369,12 +369,12 @@
 // Cache ID
 `define L3CACHE_ID              0
 
-// Block size in bytes
-`define L3CACHE_LINE_SIZE       `MEM_BLOCK_SIZE
-
 // Word size in bytes
 `define L3WORD_SIZE             `L2CACHE_LINE_SIZE
 
+// Block size in bytes
+`define L3CACHE_LINE_SIZE       (`L3_ENABLE ? `MEM_BLOCK_SIZE : `L3WORD_SIZE)
+
 // Input request tag bits
 `define L3CORE_TAG_WIDTH        (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))