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cache's core response queue size control

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This commit is contained in:
Blaise Tine
2021-07-16 13:09:29 -07:00
parent a8248b334c
commit 53b3d42908
7 changed files with 51 additions and 12 deletions
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1
hw/rtl/VX_cluster.v
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@@ -90,6 +90,7 @@ module VX_cluster #(
.WORD_SIZE (`L2WORD_SIZE), .WORD_SIZE (`L2WORD_SIZE),
.NUM_REQS (`L2NUM_REQS), .NUM_REQS (`L2NUM_REQS),
.CREQ_SIZE (`L2CREQ_SIZE), .CREQ_SIZE (`L2CREQ_SIZE),
.CRSQ_SIZE (`L2CRSQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE), .MSHR_SIZE (`L2MSHR_SIZE),
.MRSQ_SIZE (`L2MRSQ_SIZE), .MRSQ_SIZE (`L2MRSQ_SIZE),
.MREQ_SIZE (`L2MREQ_SIZE), .MREQ_SIZE (`L2MREQ_SIZE),

33
hw/rtl/VX_config.vh
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@@ -251,6 +251,11 @@
`define ICREQ_SIZE 4 `define ICREQ_SIZE 4
`endif `endif
// Core Response Queue Size
`ifndef ICRSQ_SIZE
`define ICRSQ_SIZE 2
`endif
// Miss Handling Register Size // Miss Handling Register Size
`ifndef IMSHR_SIZE `ifndef IMSHR_SIZE
`define IMSHR_SIZE `NUM_WARPS `define IMSHR_SIZE `NUM_WARPS
@@ -288,6 +293,11 @@
`define DCREQ_SIZE 4 `define DCREQ_SIZE 4
`endif `endif
// Core Response Queue Size
`ifndef DCRSQ_SIZE
`define DCRSQ_SIZE 2
`endif
// Miss Handling Register Size // Miss Handling Register Size
`ifndef DMSHR_SIZE `ifndef DMSHR_SIZE
`define DMSHR_SIZE `LSUQ_SIZE `define DMSHR_SIZE `LSUQ_SIZE
@@ -325,6 +335,11 @@
`define SCREQ_SIZE 4 `define SCREQ_SIZE 4
`endif `endif
// Core Response Queue Size
`ifndef SCRSQ_SIZE
`define SCRSQ_SIZE 2
`endif
// L2cache Configurable Knobs ///////////////////////////////////////////////// // L2cache Configurable Knobs /////////////////////////////////////////////////
// Size of cache in bytes // Size of cache in bytes
@@ -342,17 +357,22 @@
`define L2CREQ_SIZE 4 `define L2CREQ_SIZE 4
`endif `endif
// Core Response Queue Size
`ifndef L2CRSQ_SIZE
`define L2CRSQ_SIZE 2
`endif
// Miss Handling Register Size // Miss Handling Register Size
`ifndef L2MSHR_SIZE `ifndef L2MSHR_SIZE
`define L2MSHR_SIZE 16 `define L2MSHR_SIZE 16
`endif `endif
// L2 Request Queue Size // Memory Request Queue Size
`ifndef L2MREQ_SIZE `ifndef L2MREQ_SIZE
`define L2MREQ_SIZE 4 `define L2MREQ_SIZE 4
`endif `endif
// L2 Response Queue Size // Memory Response Queue Size
`ifndef L2MRSQ_SIZE `ifndef L2MRSQ_SIZE
`define L2MRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2)) `define L2MRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2))
`endif `endif
@@ -374,17 +394,22 @@
`define L3CREQ_SIZE 4 `define L3CREQ_SIZE 4
`endif `endif
// Core Response Queue Size
`ifndef L3CRSQ_SIZE
`define L3CRSQ_SIZE 2
`endif
// Miss Handling Register Size // Miss Handling Register Size
`ifndef L3MSHR_SIZE `ifndef L3MSHR_SIZE
`define L3MSHR_SIZE 16 `define L3MSHR_SIZE 16
`endif `endif
// L3 Request Queue Size // Memory Request Queue Size
`ifndef L3MREQ_SIZE `ifndef L3MREQ_SIZE
`define L3MREQ_SIZE 4 `define L3MREQ_SIZE 4
`endif `endif
// L3 Response Queue Size // Memory Response Queue Size
`ifndef L3MRSQ_SIZE `ifndef L3MRSQ_SIZE
`define L3MRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2)) `define L3MRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2))
`endif `endif

3
hw/rtl/VX_mem_unit.v
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@@ -74,6 +74,7 @@ module VX_mem_unit # (
.WORD_SIZE (`IWORD_SIZE), .WORD_SIZE (`IWORD_SIZE),
.NUM_REQS (1), .NUM_REQS (1),
.CREQ_SIZE (`ICREQ_SIZE), .CREQ_SIZE (`ICREQ_SIZE),
.CRSQ_SIZE (`ICRSQ_SIZE),
.MSHR_SIZE (`IMSHR_SIZE), .MSHR_SIZE (`IMSHR_SIZE),
.MRSQ_SIZE (`IMRSQ_SIZE), .MRSQ_SIZE (`IMRSQ_SIZE),
.MREQ_SIZE (`IMREQ_SIZE), .MREQ_SIZE (`IMREQ_SIZE),
@@ -132,6 +133,7 @@ module VX_mem_unit # (
.WORD_SIZE (`DWORD_SIZE), .WORD_SIZE (`DWORD_SIZE),
.NUM_REQS (`DNUM_REQS), .NUM_REQS (`DNUM_REQS),
.CREQ_SIZE (`DCREQ_SIZE), .CREQ_SIZE (`DCREQ_SIZE),
.CRSQ_SIZE (`DCRSQ_SIZE),
.MSHR_SIZE (`DMSHR_SIZE), .MSHR_SIZE (`DMSHR_SIZE),
.MRSQ_SIZE (`DMRSQ_SIZE), .MRSQ_SIZE (`DMRSQ_SIZE),
.MREQ_SIZE (`DMREQ_SIZE), .MREQ_SIZE (`DMREQ_SIZE),
@@ -217,6 +219,7 @@ module VX_mem_unit # (
.WORD_SIZE (`SWORD_SIZE), .WORD_SIZE (`SWORD_SIZE),
.NUM_REQS (`SNUM_REQS), .NUM_REQS (`SNUM_REQS),
.CREQ_SIZE (`SCREQ_SIZE), .CREQ_SIZE (`SCREQ_SIZE),
.CRSQ_SIZE (`SCRSQ_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE),
.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET) .BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)

1
hw/rtl/Vortex.v
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@@ -88,6 +88,7 @@ module Vortex (
.WORD_SIZE (`L3WORD_SIZE), .WORD_SIZE (`L3WORD_SIZE),
.NUM_REQS (`L3NUM_REQS), .NUM_REQS (`L3NUM_REQS),
.CREQ_SIZE (`L3CREQ_SIZE), .CREQ_SIZE (`L3CREQ_SIZE),
.CRSQ_SIZE (`L3CRSQ_SIZE),
.MSHR_SIZE (`L3MSHR_SIZE), .MSHR_SIZE (`L3MSHR_SIZE),
.MRSQ_SIZE (`L3MRSQ_SIZE), .MRSQ_SIZE (`L3MRSQ_SIZE),
.MREQ_SIZE (`L3MREQ_SIZE), .MREQ_SIZE (`L3MREQ_SIZE),

7
hw/rtl/cache/VX_bank.v vendored
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@@ -20,6 +20,8 @@ module VX_bank #(
// Core Request Queue Size // Core Request Queue Size
parameter CREQ_SIZE = 1, parameter CREQ_SIZE = 1,
// Core Response Queue Size
parameter CRSQ_SIZE = 1,
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
parameter MSHR_SIZE = 1, parameter MSHR_SIZE = 1,
// Memory Request Queue Size // Memory Request Queue Size
@@ -474,8 +476,9 @@ module VX_bank #(
assign crsq_data = rdata_st1; assign crsq_data = rdata_st1;
end end
VX_skid_buffer #( VX_elastic_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS) .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.SIZE (CRSQ_SIZE)
) core_rsp_req ( ) core_rsp_req (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

9
hw/rtl/cache/VX_cache.v vendored
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@@ -18,13 +18,15 @@ module VX_cache #(
parameter WORD_SIZE = 4, parameter WORD_SIZE = 4,
// Core Request Queue Size // Core Request Queue Size
parameter CREQ_SIZE = 4, parameter CREQ_SIZE = 2,
// Core Response Queue Size
parameter CRSQ_SIZE = 2,
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
parameter MSHR_SIZE = 8, parameter MSHR_SIZE = 8,
// Memory Response Queue Size // Memory Response Queue Size
parameter MRSQ_SIZE = 4, parameter MRSQ_SIZE = 4,
// Memory Request Queue Size // Memory Request Queue Size
parameter MREQ_SIZE = 4, parameter MREQ_SIZE = 2,
// Enable cache writeable // Enable cache writeable
parameter WRITE_ENABLE = 1, parameter WRITE_ENABLE = 1,
@@ -250,7 +252,7 @@ module VX_cache #(
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH), .DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE), .SIZE (MRSQ_SIZE),
.BUFFERED (1) .BUFFERED (MRSQ_SIZE > 2)
) mem_rsp_queue ( ) mem_rsp_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -436,6 +438,7 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE), .WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS), .NUM_REQS (NUM_REQS),
.CREQ_SIZE (CREQ_SIZE), .CREQ_SIZE (CREQ_SIZE),
.CRSQ_SIZE (CRSQ_SIZE),
.MSHR_SIZE (MSHR_SIZE), .MSHR_SIZE (MSHR_SIZE),
.MREQ_SIZE (MREQ_SIZE), .MREQ_SIZE (MREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE), .WRITE_ENABLE (WRITE_ENABLE),

9
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -13,7 +13,9 @@ module VX_shared_mem #(
parameter NUM_REQS = 4, parameter NUM_REQS = 4,
// Core Request Queue Size // Core Request Queue Size
parameter CREQ_SIZE = 8, parameter CREQ_SIZE = 2,
// Core Response Queue Size
parameter CRSQ_SIZE = 2,
// size of tag id in core request tag // size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 8, parameter CORE_TAG_ID_BITS = 8,
@@ -240,8 +242,9 @@ module VX_shared_mem #(
assign crsq_in_valid = creq_out_valid && per_bank_req_has_reads; assign crsq_in_valid = creq_out_valid && per_bank_req_has_reads;
VX_skid_buffer #( VX_elastic_buffer #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH) .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH),
.SIZE (CRSQ_SIZE)
) core_rsp_req ( ) core_rsp_req (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),