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cache's core response queue size control

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This commit is contained in:
Blaise Tine
2021-07-16 13:09:29 -07:00
parent a8248b334c
commit 53b3d42908
7 changed files with 51 additions and 12 deletions
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3
hw/rtl/VX_mem_unit.v
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@@ -74,6 +74,7 @@ module VX_mem_unit # (
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQS (1),
.CREQ_SIZE (`ICREQ_SIZE),
.CRSQ_SIZE (`ICRSQ_SIZE),
.MSHR_SIZE (`IMSHR_SIZE),
.MRSQ_SIZE (`IMRSQ_SIZE),
.MREQ_SIZE (`IMREQ_SIZE),
@@ -132,6 +133,7 @@ module VX_mem_unit # (
.WORD_SIZE (`DWORD_SIZE),
.NUM_REQS (`DNUM_REQS),
.CREQ_SIZE (`DCREQ_SIZE),
.CRSQ_SIZE (`DCRSQ_SIZE),
.MSHR_SIZE (`DMSHR_SIZE),
.MRSQ_SIZE (`DMRSQ_SIZE),
.MREQ_SIZE (`DMREQ_SIZE),
@@ -217,6 +219,7 @@ module VX_mem_unit # (
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQS (`SNUM_REQS),
.CREQ_SIZE (`SCREQ_SIZE),
.CRSQ_SIZE (`SCRSQ_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE),
.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)