Using verilog For-loops + Passing all tests

2019-03-30 22:14:44 -04:00
parent a3a3b21de7
commit 52a839f84d
12 changed files with 2379 additions and 587 deletions
--- a/rtl/VX_define.h
+++ b/rtl/VX_define.h
@@ -1,8 +1,7 @@


-#define NT 2
-#define NT_M1 1
-#define NT_T2_M1 3
+#define NT 5
+#define NT_M1 4

 #define R_INST 51
 #define L_INST 3