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minor build fixes

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This commit is contained in:
Blaise Tine
2020-03-27 20:56:18 -04:00
parent 5a5c9f3981
commit 51fd8974a9
6 changed files with 18 additions and 714 deletions
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2
driver/sw/rtlsim/Makefile
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@@ -1,7 +1,7 @@
#CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors #CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors
CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors
#USE_MULTICORE=1 USE_MULTICORE=1
CFLAGS += -I../../include -I../../../../rtl/simulate CFLAGS += -I../../include -I../../../../rtl/simulate

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driver/tests/demo/demo
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4
rtl/Makefile
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@@ -5,8 +5,8 @@ INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterface
SINGLE_CORE=Vortex.v SINGLE_CORE=Vortex.v
MULTI_CORE=Vortex_SOC.v MULTI_CORE=Vortex_SOC.v
EXE=--exe ./simulate/test_bench.cpp EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
MULTI_EXE=--exe ./simulate/multi_test_bench.cpp MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
COMP=--compiler gcc --language 1800-2009 COMP=--compiler gcc --language 1800-2009

2
rtl/simulate/Vortex.cpp
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@@ -291,8 +291,6 @@ void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) {
} }
bool Vortex::simulate() { bool Vortex::simulate() {
this->wait(50);
// reset the device // reset the device
this->reset(); this->reset();

398
rtl/simulate/Vortex.h
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@@ -20,13 +20,6 @@
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#endif #endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
typedef struct typedef struct
{ {
int cycles_left; int cycles_left;
@@ -41,11 +34,17 @@ class Vortex
Vortex(RAM* ram); Vortex(RAM* ram);
~Vortex(); ~Vortex();
bool simulate(); bool simulate();
void step();
void reset();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool is_busy();
private: private:
void print_stats(bool = true); void print_stats(bool = true);
bool ibus_driver(); bool ibus_driver();
bool dbus_driver(); bool dbus_driver();
void io_handler(); void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM* ram; RAM* ram;
@@ -79,387 +78,4 @@ class Vortex
#ifdef VCD_OUTPUT #ifdef VCD_OUTPUT
VerilatedVcdC *m_trace; VerilatedVcdC *m_trace;
#endif #endif
}; };
Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex::ibus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->I_dram_req_vec.size(); i++)
{
if (this->I_dram_req_vec[i].cycles_left > 0)
{
this->I_dram_req_vec[i].cycles_left -= 1;
}
if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->I_dram_req)
{
// std::cout << "Icache Dram Request received!\n";
if (vortex->I_dram_req_read)
{
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->I_dram_expected_lat;
dram_req.data_length = vortex->I_dram_req_size / 4;
dram_req.base_addr = vortex->I_dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->I_dram_req_vec.push_back(dram_req);
}
if (vortex->I_dram_req_write)
{
unsigned base_addr = vortex->I_dram_req_addr;
unsigned data_length = vortex->I_dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->I_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->I_dram_fill_accept && dequeue_valid)
{
// std::cout << "Icache Dram Response Sending...!\n";
vortex->I_dram_fill_rsp = 1;
vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++)
{
vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
}
free(this->I_dram_req_vec[dequeue_index].data);
this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->I_dram_fill_rsp = 0;
vortex->I_dram_fill_rsp_addr = 0;
}
return false;
}
void Vortex::io_handler()
{
// std::cout << "Checking\n";
if (vortex->io_valid)
{
uint32_t data_write = (uint32_t) vortex->io_data;
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
bool Vortex::dbus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++)
{
if (this->dram_req_vec[i].cycles_left > 0)
{
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->dram_req)
{
if (vortex->dram_req_read)
{
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->dram_expected_lat;
dram_req.data_length = vortex->dram_req_size / 4;
dram_req.base_addr = vortex->dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->dram_req_write)
{
unsigned base_addr = vortex->dram_req_addr;
unsigned data_length = vortex->dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->dram_fill_accept && dequeue_valid)
{
vortex->dram_fill_rsp = 1;
vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
{
vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->dram_fill_rsp = 0;
vortex->dram_fill_rsp_addr = 0;
}
return false;
}
bool Vortex::simulate()
{
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vortex->clk = 1;
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vortex->clk = 0;
vortex->eval();
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++time_stamp;
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram->getWord(0, &status);
this->print_stats();
return (status == 1);
// return (1 == 1);
}

326
rtl/simulate/Vortex_SOC.h
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@@ -19,13 +19,6 @@
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#endif #endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
typedef struct typedef struct
{ {
int cycles_left; int cycles_left;
@@ -40,11 +33,17 @@ class Vortex_SOC
Vortex_SOC(RAM* ram); Vortex_SOC(RAM* ram);
~Vortex_SOC(); ~Vortex_SOC();
bool simulate(); bool simulate();
void step();
void reset();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool is_busy();
private: private:
void print_stats(bool = true); void print_stats(bool = true);
bool ibus_driver(); bool ibus_driver();
bool dbus_driver(); bool dbus_driver();
void io_handler(); void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM* ram; RAM* ram;
@@ -77,313 +76,4 @@ class Vortex_SOC
#ifdef VCD_OUTPUT #ifdef VCD_OUTPUT
VerilatedVcdC *m_trace; VerilatedVcdC *m_trace;
#endif #endif
}; };
Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex_SOC;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex_SOC::~Vortex_SOC()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex_SOC::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex_SOC::ibus_driver()
{
return false;
}
void Vortex_SOC::io_handler()
{
// std::cout << "Checking\n";
for (int c = 0; c < vortex->number_cores; c++)
{
if (vortex->io_valid[c])
{
uint32_t data_write = (uint32_t) vortex->io_data[c];
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
}
bool Vortex_SOC::dbus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++)
{
if (this->dram_req_vec[i].cycles_left > 0)
{
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->out_dram_req)
{
if (vortex->out_dram_req_read)
{
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->out_dram_expected_lat;
dram_req.data_length = vortex->out_dram_req_size / 4;
dram_req.base_addr = vortex->out_dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->out_dram_req_write)
{
unsigned base_addr = vortex->out_dram_req_addr;
unsigned data_length = vortex->out_dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->out_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->out_dram_fill_accept && dequeue_valid)
{
vortex->out_dram_fill_rsp = 1;
vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
{
vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->out_dram_fill_rsp = 0;
vortex->out_dram_fill_rsp_addr = 0;
}
return false;
}
bool Vortex_SOC::simulate()
{
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vortex->clk = 1;
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vortex->clk = 0;
vortex->eval();
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++time_stamp;
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
int status = 0;
// int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram->getWord(0, &status);
this->print_stats();
return (status == 1);
// return (1 == 1);
}