Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

models/memory/cln28hpm/convertToDBAll.csh

@@ -0,0 +1,14 @@
+#! /bin/csh
+
+setenv SNPSLMD_LICENSE_FILE 1910@ece-winlic.ece.gatech.edu
+setenv PATH "${PATH}:/tools/synopsys/synthesis/j201409sp3/bin"
+setenv SYNOPSYS /tools/synopsys/synthesis/j201409sp3
+
+foreach ram (`ls`)
+	if ( -d ./$ram ) then
+		echo $ram
+		cd $ram
+		lc_shell -f ../convert_lib_to_db.tcl
+		cd ..
+	endif
+end

models/memory/cln28hpm/convert_lib_to_db.tcl

@@ -0,0 +1,13 @@
+set SOURCE_FILES [glob *.lib]
+foreach FILE ${SOURCE_FILES} {
+    read_lib $FILE
+    redirect -variable CURR_LIB {get_lib}
+
+    set CURR_LIB [string range $CURR_LIB 2 end-3] 
+    set CURR_LIB [lindex  $CURR_LIB 0]
+    set FILENAME [string range $FILE 0 end-4]
+    write_lib $CURR_LIB -output ${FILENAME}.db
+    remove_lib $CURR_LIB
+}
+
+exit