fixed gpr_ram bug + io bus arbitration
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@@ -12,24 +12,19 @@ module VX_gpr_ram (
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output reg [`NUM_THREADS-1:0][31:0] q1,
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output reg [`NUM_THREADS-1:0][31:0] q2
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);
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// Thread Byte Bit
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logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
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reg [`NUM_THREADS-1:0][31:0] ram[31:0];
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integer i;
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`UNUSED_VAR(reset)
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always @(posedge clk) begin
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if (reset) begin
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//--
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end else begin
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if (we) begin
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integer i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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if (be[i]) begin
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ram[waddr][i][0] <= wdata[i][7:0];
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ram[waddr][i][1] <= wdata[i][15:8];
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ram[waddr][i][2] <= wdata[i][23:16];
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ram[waddr][i][3] <= wdata[i][31:24];
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end
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if (we) begin
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for (i = 0; i < `NUM_THREADS; i++) begin
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if (be[i]) begin
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ram[waddr][i] <= wdata[i];
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end
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end
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end
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end
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end
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