fixed regression bug with Vortex.v model hanging issue
This commit is contained in:
108
rtl/VX_define.v
108
rtl/VX_define.v
@@ -6,12 +6,15 @@
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`ifndef NT
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`ifndef NT
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`define NT 4
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`define NT 4
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`endif
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`endif
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`ifndef NW
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`ifndef NW
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`define NW 8
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`define NW 8
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`endif
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`endif
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`ifndef NUMBER_CORES_PER_CLUSTER
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`ifndef NUMBER_CORES_PER_CLUSTER
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`define NUMBER_CORES_PER_CLUSTER 2
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`define NUMBER_CORES_PER_CLUSTER 2
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`endif
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`endif
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`ifndef NUMBER_CLUSTERS
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`ifndef NUMBER_CLUSTERS
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`define NUMBER_CLUSTERS 1
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`define NUMBER_CLUSTERS 1
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`endif
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`endif
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@@ -160,26 +163,32 @@
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`ifndef DCACHE_SIZE_BYTES
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`ifndef DCACHE_SIZE_BYTES
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`define DCACHE_SIZE_BYTES 4096
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`define DCACHE_SIZE_BYTES 4096
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`endif
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`endif
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// Size of line inside a bank in bytes
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// Size of line inside a bank in bytes
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`ifndef DBANK_LINE_SIZE_BYTES
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`ifndef DBANK_LINE_SIZE_BYTES
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`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`endif
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`endif
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// Number of banks {1, 2, 4, 8,...}
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// Number of banks {1, 2, 4, 8,...}
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`ifndef DNUMBER_BANKS
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`ifndef DNUMBER_BANKS
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`define DNUMBER_BANKS 8
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`define DNUMBER_BANKS 8
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`endif
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`endif
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// Size of a word in bytes
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// Size of a word in bytes
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`ifndef DWORD_SIZE_BYTES
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`ifndef DWORD_SIZE_BYTES
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`define DWORD_SIZE_BYTES 4
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`define DWORD_SIZE_BYTES 4
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`endif
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef DNUMBER_REQUESTS
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`ifndef DNUMBER_REQUESTS
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`define DNUMBER_REQUESTS `NT
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`define DNUMBER_REQUESTS `NT
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`endif
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef DSTAGE_1_CYCLES
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`ifndef DSTAGE_1_CYCLES
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`define DSTAGE_1_CYCLES 2
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`define DSTAGE_1_CYCLES 1
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`endif
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`endif
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// Function ID
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// Function ID
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`ifndef DFUNC_ID
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`ifndef DFUNC_ID
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`define DFUNC_ID 0
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`define DFUNC_ID 0
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@@ -235,7 +244,7 @@
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// Fill Invalidator Size {Fill invalidator must be active}
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef DFILL_INVALIDAOR_SIZE
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`ifndef DFILL_INVALIDAOR_SIZE
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`define DFILL_INVALIDAOR_SIZE 16
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`define DFILL_INVALIDAOR_SIZE 0
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`endif
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`endif
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// Dram knobs
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// Dram knobs
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@@ -253,26 +262,32 @@
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`ifndef ICACHE_SIZE_BYTES
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`ifndef ICACHE_SIZE_BYTES
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`define ICACHE_SIZE_BYTES 1024
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`define ICACHE_SIZE_BYTES 1024
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`endif
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`endif
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// Size of line inside a bank in bytes
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// Size of line inside a bank in bytes
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`ifndef IBANK_LINE_SIZE_BYTES
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`ifndef IBANK_LINE_SIZE_BYTES
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`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`endif
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`endif
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// Number of banks {1, 2, 4, 8,...}
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// Number of banks {1, 2, 4, 8,...}
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`ifndef INUMBER_BANKS
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`ifndef INUMBER_BANKS
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`define INUMBER_BANKS 8
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`define INUMBER_BANKS 8
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`endif
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`endif
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// Size of a word in bytes
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// Size of a word in bytes
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`ifndef IWORD_SIZE_BYTES
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`ifndef IWORD_SIZE_BYTES
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`define IWORD_SIZE_BYTES 4
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`define IWORD_SIZE_BYTES 4
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`endif
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef INUMBER_REQUESTS
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`ifndef INUMBER_REQUESTS
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`define INUMBER_REQUESTS 1
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`define INUMBER_REQUESTS 1
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`endif
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef ISTAGE_1_CYCLES
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`ifndef ISTAGE_1_CYCLES
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`define ISTAGE_1_CYCLES 2
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`define ISTAGE_1_CYCLES 1
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`endif
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`endif
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// Function ID
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// Function ID
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`ifndef IFUNC_ID
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`ifndef IFUNC_ID
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`define IFUNC_ID 1
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`define IFUNC_ID 1
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@@ -282,45 +297,55 @@
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`ifndef IBANK_LINE_SIZE_WORDS
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`ifndef IBANK_LINE_SIZE_WORDS
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`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
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`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
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`endif
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`endif
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`ifndef IBANK_LINE_SIZE_RNG
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`ifndef IBANK_LINE_SIZE_RNG
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`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
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`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
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`endif
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`endif
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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// Core Request Queue Size
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`ifndef IREQQ_SIZE
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`ifndef IREQQ_SIZE
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`define IREQQ_SIZE `NW
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`define IREQQ_SIZE `NW
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`endif
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`endif
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// Miss Reserv Queue Knob
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// Miss Reserv Queue Knob
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`ifndef IMRVQ_SIZE
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`ifndef IMRVQ_SIZE
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`define IMRVQ_SIZE `IREQQ_SIZE
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`define IMRVQ_SIZE `IREQQ_SIZE
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`endif
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`endif
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// Dram Fill Rsp Queue Size
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// Dram Fill Rsp Queue Size
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`ifndef IDFPQ_SIZE
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`ifndef IDFPQ_SIZE
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`define IDFPQ_SIZE 2
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`define IDFPQ_SIZE 2
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`endif
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`endif
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// Snoop Req Queue
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// Snoop Req Queue
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`ifndef ISNRQ_SIZE
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`ifndef ISNRQ_SIZE
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`define ISNRQ_SIZE 8
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`define ISNRQ_SIZE 8
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`endif
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`endif
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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// Core Writeback Queue Size
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`ifndef ICWBQ_SIZE
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`ifndef ICWBQ_SIZE
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`define ICWBQ_SIZE `IREQQ_SIZE
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`define ICWBQ_SIZE `IREQQ_SIZE
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`endif
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`endif
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// Dram Writeback Queue Size
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// Dram Writeback Queue Size
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`ifndef IDWBQ_SIZE
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`ifndef IDWBQ_SIZE
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`define IDWBQ_SIZE 0
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`define IDWBQ_SIZE 16
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`endif
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`endif
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// Dram Fill Req Queue Size
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// Dram Fill Req Queue Size
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`ifndef IDFQQ_SIZE
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`ifndef IDFQQ_SIZE
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`define IDFQQ_SIZE `IREQQ_SIZE
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`define IDFQQ_SIZE `IREQQ_SIZE
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`endif
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`endif
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// Lower Level Cache Hit Queue Size
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// Lower Level Cache Hit Queue Size
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`ifndef ILLVQ_SIZE
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`ifndef ILLVQ_SIZE
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`define ILLVQ_SIZE 0
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`define ILLVQ_SIZE 16
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`endif
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`endif
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// Fill Forward SNP Queue
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// Fill Forward SNP Queue
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`ifndef IFFSQ_SIZE
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`ifndef IFFSQ_SIZE
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`define IFFSQ_SIZE 8
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`define IFFSQ_SIZE 8
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@@ -328,7 +353,7 @@
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// Fill Invalidator Size {Fill invalidator must be active}
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef IFILL_INVALIDAOR_SIZE
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`ifndef IFILL_INVALIDAOR_SIZE
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`define IFILL_INVALIDAOR_SIZE 16
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`define IFILL_INVALIDAOR_SIZE 0
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`endif
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`endif
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// Dram knobs
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// Dram knobs
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@@ -345,26 +370,32 @@
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`ifndef SCACHE_SIZE_BYTES
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`ifndef SCACHE_SIZE_BYTES
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`define SCACHE_SIZE_BYTES 1024
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`define SCACHE_SIZE_BYTES 1024
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`endif
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`endif
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// Size of line inside a bank in bytes
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// Size of line inside a bank in bytes
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`ifndef SBANK_LINE_SIZE_BYTES
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`ifndef SBANK_LINE_SIZE_BYTES
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`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`endif
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`endif
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// Number of banks {1, 2, 4, 8,...}
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// Number of banks {1, 2, 4, 8,...}
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`ifndef SNUMBER_BANKS
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`ifndef SNUMBER_BANKS
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`define SNUMBER_BANKS 8
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`define SNUMBER_BANKS 8
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`endif
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`endif
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// Size of a word in bytes
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// Size of a word in bytes
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`ifndef SWORD_SIZE_BYTES
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`ifndef SWORD_SIZE_BYTES
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`define SWORD_SIZE_BYTES 4
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`define SWORD_SIZE_BYTES 4
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`endif
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef SNUMBER_REQUESTS
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`ifndef SNUMBER_REQUESTS
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`define SNUMBER_REQUESTS `NT
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`define SNUMBER_REQUESTS `NT
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`endif
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef SSTAGE_1_CYCLES
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`ifndef SSTAGE_1_CYCLES
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`define SSTAGE_1_CYCLES 2
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`define SSTAGE_1_CYCLES 1
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`endif
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`endif
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// Function ID
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// Function ID
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`ifndef SFUNC_ID
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`ifndef SFUNC_ID
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`define SFUNC_ID 2
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`define SFUNC_ID 2
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@@ -374,53 +405,63 @@
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`ifndef SBANK_LINE_SIZE_WORDS
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`ifndef SBANK_LINE_SIZE_WORDS
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`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
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`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
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`endif
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`endif
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`ifndef SBANK_LINE_SIZE_RNG
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`ifndef SBANK_LINE_SIZE_RNG
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`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0
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`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0
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`endif
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`endif
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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// Core Request Queue Size
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`ifndef SREQQ_SIZE
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`ifndef SREQQ_SIZE
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`define SREQQ_SIZE `NW
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`define SREQQ_SIZE `NW
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`endif
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`endif
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// Miss Reserv Queue Knob
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// Miss Reserv Queue Knob
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`ifndef SMRVQ_SIZE
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`ifndef SMRVQ_SIZE
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`define SMRVQ_SIZE `SREQQ_SIZE
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`define SMRVQ_SIZE `SREQQ_SIZE
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`endif
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`endif
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// Dram Fill Rsp Queue Size
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// Dram Fill Rsp Queue Size
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`ifndef SDFPQ_SIZE
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`ifndef SDFPQ_SIZE
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`define SDFPQ_SIZE 0
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`define SDFPQ_SIZE 16
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`endif
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`endif
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// Snoop Req Queue
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// Snoop Req Queue
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`ifndef SSNRQ_SIZE
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`ifndef SSNRQ_SIZE
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`define SSNRQ_SIZE 0
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`define SSNRQ_SIZE 16
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`endif
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`endif
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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// Core Writeback Queue Size
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`ifndef SCWBQ_SIZE
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`ifndef SCWBQ_SIZE
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`define SCWBQ_SIZE `SREQQ_SIZE
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`define SCWBQ_SIZE `SREQQ_SIZE
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`endif
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`endif
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// Dram Writeback Queue Size
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// Dram Writeback Queue Size
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`ifndef SDWBQ_SIZE
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`ifndef SDWBQ_SIZE
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`define SDWBQ_SIZE 0
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`define SDWBQ_SIZE 16
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`endif
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`endif
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// Dram Fill Req Queue Size
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// Dram Fill Req Queue Size
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`ifndef SDFQQ_SIZE
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`ifndef SDFQQ_SIZE
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`define SDFQQ_SIZE 0
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`define SDFQQ_SIZE 16
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`endif
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`endif
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// Lower Level Cache Hit Queue Size
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// Lower Level Cache Hit Queue Size
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||||||
`ifndef SLLVQ_SIZE
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`ifndef SLLVQ_SIZE
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`define SLLVQ_SIZE 0
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`define SLLVQ_SIZE 16
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`endif
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`endif
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||||||
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// Fill Forward SNP Queue
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// Fill Forward SNP Queue
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||||||
`ifndef SFFSQ_SIZE
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`ifndef SFFSQ_SIZE
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`define SFFSQ_SIZE 0
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`define SFFSQ_SIZE 16
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`endif
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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// Fill Invalidator Size {Fill invalidator must be active}
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||||||
`ifndef SFILL_INVALIDAOR_SIZE
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`ifndef SFILL_INVALIDAOR_SIZE
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`define SFILL_INVALIDAOR_SIZE 16
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`define SFILL_INVALIDAOR_SIZE 0
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`endif
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`endif
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// Dram knobs
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// Dram knobs
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||||||
@@ -439,26 +480,32 @@
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`ifndef LLCACHE_SIZE_BYTES
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`ifndef LLCACHE_SIZE_BYTES
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`define LLCACHE_SIZE_BYTES 1024
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`define LLCACHE_SIZE_BYTES 1024
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`endif
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`endif
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// Size of line inside a bank in bytes
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// Size of line inside a bank in bytes
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||||||
`ifndef LLBANK_LINE_SIZE_BYTES
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`ifndef LLBANK_LINE_SIZE_BYTES
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`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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||||||
`endif
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`endif
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||||||
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// Number of banks {1, 2, 4, 8,...}
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// Number of banks {1, 2, 4, 8,...}
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||||||
`ifndef LLNUMBER_BANKS
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`ifndef LLNUMBER_BANKS
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`define LLNUMBER_BANKS 8
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`define LLNUMBER_BANKS 8
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`endif
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`endif
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// Size of a word in bytes
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// Size of a word in bytes
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||||||
`ifndef LLWORD_SIZE_BYTES
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`ifndef LLWORD_SIZE_BYTES
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`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES)
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`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES)
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`endif
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`endif
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||||||
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef LLNUMBER_REQUESTS
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`ifndef LLNUMBER_REQUESTS
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`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
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`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
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`endif
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`endif
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||||||
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// Number of cycles to complete stage 1 (read from memory)
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// Number of cycles to complete stage 1 (read from memory)
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||||||
`ifndef LLSTAGE_1_CYCLES
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`ifndef LLSTAGE_1_CYCLES
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`define LLSTAGE_1_CYCLES 2
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`define LLSTAGE_1_CYCLES 1
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`endif
|
`endif
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// Function ID
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// Function ID
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`define LLFUNC_ID 3
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`define LLFUNC_ID 3
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@@ -466,6 +513,7 @@
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`ifndef LLBANK_LINE_SIZE_WORDS
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`ifndef LLBANK_LINE_SIZE_WORDS
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`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES)
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`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES)
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`endif
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`endif
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||||||
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`ifndef LLBANK_LINE_SIZE_RNG
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`ifndef LLBANK_LINE_SIZE_RNG
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`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
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`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
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`endif
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`endif
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@@ -475,14 +523,17 @@
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`ifndef LLREQQ_SIZE
|
`ifndef LLREQQ_SIZE
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`define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
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`define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
|
||||||
`endif
|
`endif
|
||||||
|
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||||||
// Miss Reserv Queue Knob
|
// Miss Reserv Queue Knob
|
||||||
`ifndef LLMRVQ_SIZE
|
`ifndef LLMRVQ_SIZE
|
||||||
`define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
|
`define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Fill Rsp Queue Size
|
// Dram Fill Rsp Queue Size
|
||||||
`ifndef LLDFPQ_SIZE
|
`ifndef LLDFPQ_SIZE
|
||||||
`define LLDFPQ_SIZE 2
|
`define LLDFPQ_SIZE 2
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Snoop Req Queue
|
// Snoop Req Queue
|
||||||
`ifndef LLSNRQ_SIZE
|
`ifndef LLSNRQ_SIZE
|
||||||
`define LLSNRQ_SIZE 8
|
`define LLSNRQ_SIZE 8
|
||||||
@@ -493,18 +544,22 @@
|
|||||||
`ifndef LLCWBQ_SIZE
|
`ifndef LLCWBQ_SIZE
|
||||||
`define LLCWBQ_SIZE `LLREQQ_SIZE
|
`define LLCWBQ_SIZE `LLREQQ_SIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Writeback Queue Size
|
// Dram Writeback Queue Size
|
||||||
`ifndef LLDWBQ_SIZE
|
`ifndef LLDWBQ_SIZE
|
||||||
`define LLDWBQ_SIZE 4
|
`define LLDWBQ_SIZE 4
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Fill Req Queue Size
|
// Dram Fill Req Queue Size
|
||||||
`ifndef LLDFQQ_SIZE
|
`ifndef LLDFQQ_SIZE
|
||||||
`define LLDFQQ_SIZE `LLREQQ_SIZE
|
`define LLDFQQ_SIZE `LLREQQ_SIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Lower Level Cache Hit Queue Size
|
// Lower Level Cache Hit Queue Size
|
||||||
`ifndef LLLLVQ_SIZE
|
`ifndef LLLLVQ_SIZE
|
||||||
`define LLLLVQ_SIZE 0
|
`define LLLLVQ_SIZE 16
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Fill Forward SNP Queue
|
// Fill Forward SNP Queue
|
||||||
`ifndef LLFFSQ_SIZE
|
`ifndef LLFFSQ_SIZE
|
||||||
`define LLFFSQ_SIZE 8
|
`define LLFFSQ_SIZE 8
|
||||||
@@ -512,7 +567,7 @@
|
|||||||
|
|
||||||
// Fill Invalidator Size {Fill invalidator must be active}
|
// Fill Invalidator Size {Fill invalidator must be active}
|
||||||
`ifndef LLFILL_INVALIDAOR_SIZE
|
`ifndef LLFILL_INVALIDAOR_SIZE
|
||||||
`define LLFILL_INVALIDAOR_SIZE 16
|
`define LLFILL_INVALIDAOR_SIZE 0
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram knobs
|
// Dram knobs
|
||||||
@@ -529,26 +584,32 @@
|
|||||||
`ifndef L3CACHE_SIZE_BYTES
|
`ifndef L3CACHE_SIZE_BYTES
|
||||||
`define L3CACHE_SIZE_BYTES 1024
|
`define L3CACHE_SIZE_BYTES 1024
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Size of line inside a bank in bytes
|
// Size of line inside a bank in bytes
|
||||||
`ifndef L3BANK_LINE_SIZE_BYTES
|
`ifndef L3BANK_LINE_SIZE_BYTES
|
||||||
`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
|
`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Number of banks {1, 2, 4, 8,...}
|
// Number of banks {1, 2, 4, 8,...}
|
||||||
`ifndef L3NUMBER_BANKS
|
`ifndef L3NUMBER_BANKS
|
||||||
`define L3NUMBER_BANKS 8
|
`define L3NUMBER_BANKS 8
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Size of a word in bytes
|
// Size of a word in bytes
|
||||||
`ifndef L3WORD_SIZE_BYTES
|
`ifndef L3WORD_SIZE_BYTES
|
||||||
`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
|
`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Number of Word requests per cycle {1, 2, 4, 8, ...}
|
// Number of Word requests per cycle {1, 2, 4, 8, ...}
|
||||||
`ifndef L3NUMBER_REQUESTS
|
`ifndef L3NUMBER_REQUESTS
|
||||||
`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS)
|
`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS)
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Number of cycles to complete stage 1 (read from memory)
|
// Number of cycles to complete stage 1 (read from memory)
|
||||||
`ifndef L3STAGE_1_CYCLES
|
`ifndef L3STAGE_1_CYCLES
|
||||||
`define L3STAGE_1_CYCLES 2
|
`define L3STAGE_1_CYCLES 1
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Function ID
|
// Function ID
|
||||||
`define L3FUNC_ID 3
|
`define L3FUNC_ID 3
|
||||||
|
|
||||||
@@ -556,23 +617,28 @@
|
|||||||
`ifndef L3BANK_LINE_SIZE_WORDS
|
`ifndef L3BANK_LINE_SIZE_WORDS
|
||||||
`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
|
`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
`ifndef L3BANK_LINE_SIZE_RNG
|
`ifndef L3BANK_LINE_SIZE_RNG
|
||||||
`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0
|
`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
|
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
|
||||||
|
|
||||||
// Core Request Queue Size
|
// Core Request Queue Size
|
||||||
`ifndef L3REQQ_SIZE
|
`ifndef L3REQQ_SIZE
|
||||||
`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS)
|
`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS)
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Miss Reserv Queue Knob
|
// Miss Reserv Queue Knob
|
||||||
`ifndef L3MRVQ_SIZE
|
`ifndef L3MRVQ_SIZE
|
||||||
`define L3MRVQ_SIZE `LLREQQ_SIZE
|
`define L3MRVQ_SIZE `LLREQQ_SIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Fill Rsp Queue Size
|
// Dram Fill Rsp Queue Size
|
||||||
`ifndef L3DFPQ_SIZE
|
`ifndef L3DFPQ_SIZE
|
||||||
`define L3DFPQ_SIZE 2
|
`define L3DFPQ_SIZE 2
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Snoop Req Queue
|
// Snoop Req Queue
|
||||||
`ifndef L3SNRQ_SIZE
|
`ifndef L3SNRQ_SIZE
|
||||||
`define L3SNRQ_SIZE 8
|
`define L3SNRQ_SIZE 8
|
||||||
@@ -583,18 +649,22 @@
|
|||||||
`ifndef L3CWBQ_SIZE
|
`ifndef L3CWBQ_SIZE
|
||||||
`define L3CWBQ_SIZE `L3REQQ_SIZE
|
`define L3CWBQ_SIZE `L3REQQ_SIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Writeback Queue Size
|
// Dram Writeback Queue Size
|
||||||
`ifndef L3DWBQ_SIZE
|
`ifndef L3DWBQ_SIZE
|
||||||
`define L3DWBQ_SIZE 4
|
`define L3DWBQ_SIZE 4
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram Fill Req Queue Size
|
// Dram Fill Req Queue Size
|
||||||
`ifndef L3DFQQ_SIZE
|
`ifndef L3DFQQ_SIZE
|
||||||
`define L3DFQQ_SIZE `L3REQQ_SIZE
|
`define L3DFQQ_SIZE `L3REQQ_SIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Lower Level Cache Hit Queue Size
|
// Lower Level Cache Hit Queue Size
|
||||||
`ifndef L3LLVQ_SIZE
|
`ifndef L3LLVQ_SIZE
|
||||||
`define L3LLVQ_SIZE 0
|
`define L3LLVQ_SIZE 0
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Fill Forward SNP Queue
|
// Fill Forward SNP Queue
|
||||||
`ifndef L3FFSQ_SIZE
|
`ifndef L3FFSQ_SIZE
|
||||||
`define L3FFSQ_SIZE 8
|
`define L3FFSQ_SIZE 8
|
||||||
@@ -602,7 +672,7 @@
|
|||||||
|
|
||||||
// Fill Invalidator Size {Fill invalidator must be active}
|
// Fill Invalidator Size {Fill invalidator must be active}
|
||||||
`ifndef L3FILL_INVALIDAOR_SIZE
|
`ifndef L3FILL_INVALIDAOR_SIZE
|
||||||
`define L3FILL_INVALIDAOR_SIZE 16
|
`define L3FILL_INVALIDAOR_SIZE 0
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Dram knobs
|
// Dram knobs
|
||||||
|
|||||||
Reference in New Issue
Block a user