scope refactoring
This commit is contained in:
Blaise Tine
161
hw/scripts/scope.json
Normal file
161
hw/scripts/scope.json
Normal file
@@ -0,0 +1,161 @@
|
||||
{
|
||||
"version": 1,
|
||||
"includes":[
|
||||
"../rtl/VX_config.vh",
|
||||
"../rtl/VX_platform.vh",
|
||||
"../rtl/VX_define.vh",
|
||||
"../rtl/cache/VX_cache_config.vh"
|
||||
],
|
||||
"parameters": {
|
||||
"L3_ENABLE": "`L3_ENABLE",
|
||||
"L2_ENABLE": "`L2_ENABLE",
|
||||
"NUM_CLUSTERS": "`NUM_CLUSTERS",
|
||||
"NUM_CORES": "`NUM_CORES",
|
||||
"DNUM_BANKS": "`DNUM_BANKS",
|
||||
"INUM_BANKS": "`INUM_BANKS",
|
||||
"SNUM_BANKS": "`SNUM_BANKS",
|
||||
"L2NUM_BANKS": "`L2NUM_BANKS",
|
||||
"L3NUM_BANKS": "`L3NUM_BANKS"
|
||||
},
|
||||
"taps": {
|
||||
"top::SCOPE_SIGNALS_AFU": {
|
||||
"!scope_dram_req_valid": 1,
|
||||
"scope_dram_req_addr": 32,
|
||||
"scope_dram_req_rw": 1,
|
||||
"scope_dram_req_byteen": "`VX_DRAM_BYTEEN_WIDTH",
|
||||
"scope_dram_req_data": "`VX_DRAM_LINE_WIDTH",
|
||||
"scope_dram_req_tag": "`VX_DRAM_TAG_WIDTH",
|
||||
"!scope_dram_req_ready": 1,
|
||||
"!scope_dram_rsp_valid": 1,
|
||||
"scope_dram_rsp_data": 128,
|
||||
"scope_dram_rsp_tag": "`VX_DRAM_TAG_WIDTH",
|
||||
"!scope_dram_rsp_ready": 1,
|
||||
"!scope_snp_req_valid": 1,
|
||||
"scope_snp_req_addr": 32,
|
||||
"scope_snp_req_invalidate": 1,
|
||||
"scope_snp_req_tag": "`VX_SNP_TAG_WIDTH",
|
||||
"!scope_snp_req_ready": 1,
|
||||
"!scope_snp_rsp_valid": 1,
|
||||
"scope_snp_rsp_tag": "`VX_SNP_TAG_WIDTH",
|
||||
"!scope_snp_rsp_ready": 1,
|
||||
"scope_busy": 1
|
||||
},
|
||||
"core::SCOPE_SIGNALS_ISTAGE": {
|
||||
"!scope_icache_req_valid": 1,
|
||||
"scope_icache_req_wid": "`NW_BITS",
|
||||
"scope_icache_req_addr": 32,
|
||||
"scope_icache_req_tag": "`ICORE_TAG_ID_BITS",
|
||||
"!scope_icache_req_ready": 1,
|
||||
"!scope_icache_rsp_valid": 1,
|
||||
"scope_icache_rsp_data": 32,
|
||||
"scope_icache_rsp_tag": "`ICORE_TAG_ID_BITS",
|
||||
"!scope_icache_rsp_ready": 1
|
||||
},
|
||||
"core::SCOPE_SIGNALS_LSU": {
|
||||
"!scope_dcache_req_valid": "`NUM_THREADS",
|
||||
"scope_dcache_req_wid": "`NW_BITS",
|
||||
"scope_dcache_req_pc": 32,
|
||||
"scope_dcache_req_addr": "`NUM_THREADS * 32",
|
||||
"scope_dcache_req_rw": 1,
|
||||
"scope_dcache_req_byteen": "`NUM_THREADS * 4",
|
||||
"scope_dcache_req_data": "`NUM_THREADS * 32",
|
||||
"scope_dcache_req_tag": "`DCORE_TAG_ID_BITS",
|
||||
"!scope_dcache_req_ready": 1,
|
||||
"!scope_dcache_rsp_valid": "`NUM_THREADS",
|
||||
"scope_dcache_rsp_data": "`NUM_THREADS * 32",
|
||||
"scope_dcache_rsp_tag": "`DCORE_TAG_ID_BITS",
|
||||
"!scope_dcache_rsp_ready": 1
|
||||
},
|
||||
"core::SCOPE_SIGNALS_ISSUE": {
|
||||
"!scope_issue_valid": 1,
|
||||
"scope_issue_wid": "`NW_BITS",
|
||||
"scope_issue_tmask": "`NUM_THREADS",
|
||||
"scope_issue_pc": 32,
|
||||
"scope_issue_ex_type": "`EX_BITS",
|
||||
"scope_issue_op_type": "`OP_BITS",
|
||||
"scope_issue_op_mod": "`MOD_BITS",
|
||||
"scope_issue_wb": 1,
|
||||
"scope_issue_rd": "`NR_BITS",
|
||||
"scope_issue_rs1": "`NR_BITS",
|
||||
"scope_issue_rs2": "`NR_BITS",
|
||||
"scope_issue_rs3": "`NR_BITS",
|
||||
"scope_issue_imm": 32,
|
||||
"scope_issue_rs1_is_pc": 1,
|
||||
"scope_issue_rs2_is_imm": 1,
|
||||
"!scope_issue_ready": 1,
|
||||
"!scope_gpr_rsp_valid": 1,
|
||||
"scope_gpr_rsp_wid": "`NW_BITS",
|
||||
"scope_gpr_rsp_pc": 32,
|
||||
"scope_gpr_rsp_a": "`NUM_THREADS * 32",
|
||||
"scope_gpr_rsp_b": "`NUM_THREADS * 32",
|
||||
"scope_gpr_rsp_c": "`NUM_THREADS * 32",
|
||||
"!scope_gpr_delay": 1,
|
||||
"!scope_writeback_valid": 1,
|
||||
"scope_writeback_wid": "`NW_BITS",
|
||||
"scope_writeback_pc": 32,
|
||||
"scope_writeback_rd": "`NR_BITS",
|
||||
"scope_writeback_data": "`NUM_THREADS * 32",
|
||||
"!scope_scoreboard_delay": 1,
|
||||
"!scope_execute_delay": 1
|
||||
},
|
||||
"core::SCOPE_SIGNALS_EXECUTE": {},
|
||||
"bank::SCOPE_SIGNALS_BANK": {
|
||||
"!scope_bank_valid_st0": 1,
|
||||
"!scope_bank_valid_st1": 1,
|
||||
"!scope_bank_valid_st2": 1,
|
||||
"scope_bank_addr_st0": 32,
|
||||
"scope_bank_addr_st1": 32,
|
||||
"scope_bank_addr_st2": 32,
|
||||
"scope_bank_is_mrvq_st1": 1,
|
||||
"scope_bank_miss_st1": 1,
|
||||
"scope_bank_dirty_st1": 1,
|
||||
"!scope_bank_force_miss_st1": 1,
|
||||
"!scope_bank_stall_pipe": 1
|
||||
}
|
||||
},
|
||||
"triggers": [
|
||||
["scope_dram_req_valid", "scope_dram_req_ready"],
|
||||
["scope_dram_rsp_valid", "scope_dram_rsp_ready"],
|
||||
["scope_snp_req_valid", "scope_snp_req_ready"],
|
||||
["scope_snp_rsp_valid", "scope_snp_rsp_ready"],
|
||||
|
||||
["scope_icache_req_valid_top", "scope_icache_req_ready_top"],
|
||||
["scope_icache_rsp_valid_top", "scope_icache_rsp_ready_top"],
|
||||
["scope_dcache_req_valid_top", "scope_dcache_req_ready_top"],
|
||||
["scope_dcache_rsp_valid_top", "scope_dcache_rsp_ready_top"],
|
||||
|
||||
["scope_bank_valid_st0_l3_top"],
|
||||
["scope_bank_valid_st1_l3_top"],
|
||||
["scope_bank_valid_st2_l3_top"],
|
||||
["scope_bank_stall_pipe_l3_top"],
|
||||
|
||||
["scope_bank_valid_st0_l2_top"],
|
||||
["scope_bank_valid_st1_l2_top"],
|
||||
["scope_bank_valid_st2_l2_top"],
|
||||
["scope_bank_stall_pipe_l2_top"],
|
||||
|
||||
["scope_bank_valid_st0_l1d_top"],
|
||||
["scope_bank_valid_st1_l1d_top"],
|
||||
["scope_bank_valid_st2_l1d_top"],
|
||||
["scope_bank_stall_pipe_l1d_top"],
|
||||
|
||||
["scope_bank_valid_st0_l1i_top"],
|
||||
["scope_bank_valid_st1_l1i_top"],
|
||||
["scope_bank_valid_st2_l1i_top"],
|
||||
["scope_bank_stall_pipe_l1i_top"],
|
||||
|
||||
["scope_bank_valid_st0_l1s_top"],
|
||||
["scope_bank_valid_st1_l1s_top"],
|
||||
["scope_bank_valid_st2_l1s_top"],
|
||||
["scope_bank_stall_pipe_l1s_top"],
|
||||
|
||||
["scope_issue_valid_top", "scope_issue_ready_top"],
|
||||
["scope_gpr_rsp_valid_top"],
|
||||
["scope_scoreboard_delay_top"],
|
||||
["scope_gpr_delay_top"],
|
||||
["scope_execute_delay_top"],
|
||||
|
||||
["scope_busy"]
|
||||
]
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user