wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

tex_unit compiler fixes

Browse Source
This commit is contained in:
Blaise Tine
2021-03-22 21:56:06 -04:00
parent 8f0198149a
commit 4de75fad31
4 changed files with 11 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/rtl/VX_execute.v
View File

@@ -80,10 +80,14 @@ module VX_execute #(
for (genvar i = 0; i < `NUM_THREADS; ++i) begin for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign lsu_tag_in[i][`LSUQ_ADDR_BITS-1:0] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS-1:0]; assign lsu_tag_in[i][`LSUQ_ADDR_BITS-1:0] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS-1:0];
assign lsu_tag_in[i][`LSUQ_ADDR_BITS+:2] = '0; assign lsu_tag_in[i][`LSUQ_ADDR_BITS+:2] = '0;
`ifdef DBG_CACHE_REQ_INFO
assign lsu_tag_in[i][(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW]; assign lsu_tag_in[i][(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW];
`endif
end end
assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0] = lsu_tag_out[`LSUQ_ADDR_BITS-1:0]; assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0] = lsu_tag_out[`LSUQ_ADDR_BITS-1:0];
`ifdef DBG_CACHE_REQ_INFO
assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW] = lsu_tag_out[(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW]; assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW] = lsu_tag_out[(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW];
`endif
`UNUSED_VAR (lsu_tag_out) `UNUSED_VAR (lsu_tag_out)
VX_tex_lsu_arb #( VX_tex_lsu_arb #(

2
hw/rtl/tex_unit/VX_tex_define.vh
View File

@@ -9,7 +9,7 @@
`define FIXED_HALF (`FIXED_ONE >> 1) `define FIXED_HALF (`FIXED_ONE >> 1)
`define FIXED_MASK (`FIXED_ONE - 1) `define FIXED_MASK (`FIXED_ONE - 1)
`define CLAMP(x,lo,hi) ((x < lo) ? lo : ((x > hi) ? hi : x)) `define CLAMP(x,lo,hi) (($signed(x) < $signed(lo)) ? lo : ((x > hi) ? hi : x))
`define BLEND_FRAC_64 8 `define BLEND_FRAC_64 8

6
hw/rtl/tex_unit/VX_tex_memory.v
View File

@@ -179,7 +179,9 @@ module VX_tex_memory #(
`ifdef DBG_CACHE_REQ_INFO `ifdef DBG_CACHE_REQ_INFO
assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, texel_idx, q_ib_waddr}}; assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, texel_idx, q_ib_waddr}};
`else `else
assign dcache_req_if.tag = {`NUM_THREADS{q_ib_waddr}}; assign dcache_req_if.tag = {`NUM_THREADS{texel_idx, q_ib_waddr}};
`UNUSED_VAR (q_req_wid)
`UNUSED_VAR (q_req_PC)
`endif `endif
// Dcache Response // Dcache Response
@@ -215,7 +217,7 @@ module VX_tex_memory #(
assign mbuf_raddr = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0]; assign mbuf_raddr = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0];
assign rsp_texel_idx = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1+:2]; assign rsp_texel_idx = dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:2];
assign rsp_is_dup = ib_dup_reqs[rsp_texel_idx]; assign rsp_is_dup = ib_dup_reqs[rsp_texel_idx];

2
hw/rtl/tex_unit/VX_tex_wrap.v
View File

@@ -14,6 +14,8 @@ module VX_tex_wrap #(
wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK); wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK);
`UNUSED_VAR (clamp)
always @(*) begin always @(*) begin
case (wrap_i) case (wrap_i)
`TEX_WRAP_CLAMP: `TEX_WRAP_CLAMP: