cache pipeline optimization - moved tag access to stage0
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@@ -192,15 +192,13 @@
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"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank, afu/vortex/cluster/core/mem_unit/smem/bank": {
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"?valid_st0": 1,
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"?valid_st1": 1,
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"?valid_st2": 1,
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"addr_st0": 32,
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"addr_st1": 32,
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"addr_st2": 32,
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"is_fill_st0": 1,
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"is_mshr_st0": 1,
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"miss_st1": 1,
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"force_miss_st1": 1,
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"dirty_st1": 1,
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"miss_st0": 1,
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"force_miss_st0": 1,
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"dirty_st0": 1,
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"mshr_push": 1,
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"?pipeline_stall": 1
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}
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