enabling 128-bit dram bus

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -45,6 +45,7 @@ module VX_cache_core_req_bank_sel #(
     output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag,
     input  wire [`BANK_READY_COUNT-1:0]             per_bank_core_req_ready
 );
+    `UNUSED_PARAM (CACHE_ID)
     `STATIC_ASSERT (NUM_REQS >= NUM_BANKS, ("invalid number of banks"));
 
     `UNUSED_VAR (clk)

hw/rtl/cache/VX_cache_core_rsp_merge.v

@@ -33,6 +33,8 @@ module VX_cache_core_rsp_merge #(
     output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0]     core_rsp_data,      
     input  wire [`CORE_REQ_TAG_COUNT-1:0]           core_rsp_ready
 );
+    `UNUSED_PARAM (CACHE_ID)
+
     if (NUM_BANKS > 1) begin
 
         reg [NUM_REQS-1:0] core_rsp_valid_unqual;