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Mem technology compiling but still reading all zeros

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This commit is contained in:
felsabbagh3
2019-10-18 16:45:42 -04:00
parent f7d826593f
commit 4cae140ac1
5 changed files with 112 additions and 94 deletions
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5
rtl/Makefile
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@@ -8,9 +8,10 @@ EXE=--exe ./simulate/test_bench.cpp
COMP=--compiler gcc COMP=--compiler gcc
WNO=-Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint --Wno-PINMISSING WNO=-Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint --Wno-PINMISSING -Wno-STMTDLY
LIB=-LDFLAGS '-L/usr/local/systemc/' # LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
CF=-CFLAGS '-std=c++11 -O3' CF=-CFLAGS '-std=c++11 -O3'

183
rtl/VX_gpr.v
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@@ -15,95 +15,104 @@ module VX_gpr (
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0)); assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
byte_enabled_simple_dual_port_ram first_ram( // byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable), // .we (write_enable),
.clk (clk), // .clk (clk),
.waddr (VX_writeback_inter.rd), // .waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1), // .raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2), // .raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid), // .be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data), // .wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data), // .q1 (out_a_reg_data),
.q2 (out_b_reg_data) // .q2 (out_b_reg_data)
); // );
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
assign write_bit_mask[curr_t] = {32{~local_write}};
end
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}}; // wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
// /* verilator lint_off PINCONNECTEMPTY */ /* verilator lint_off PINCONNECTEMPTY */
// rf2_32x128_wm1 first_ram ( rf2_32x128_wm1 first_ram (
// .CENYA(), .CENYA(),
// .AYA(), .AYA(),
// .CENYB(), .CENYB(),
// .WENYB(), .WENYB(),
// .AYB(), .AYB(),
// .QA(out_a_reg_data), .QA(out_a_reg_data),
// .SOA(), .SOA(),
// .SOB(), .SOB(),
// .CLKA(clk), .CLKA(clk),
// .CENA(1'b0), .CENA(1'b0),
// .AA(VX_gpr_read.rs1), .AA(VX_gpr_read.rs1),
// .CLKB(clk), .CLKB(clk),
// .CENB(1'b0), .CENB(1'b0),
// .WENB(write_bit_mask), .WENB(write_bit_mask),
// .AB(VX_writeback_inter.rd), .AB(VX_writeback_inter.rd),
// .DB(VX_writeback_inter.write_data), .DB(VX_writeback_inter.write_data),
// .EMAA(3'b011), .EMAA(3'b011),
// .EMASA(1'b0), .EMASA(1'b0),
// .EMAB(3'b011), .EMAB(3'b011),
// .TENA(1'b1), .TENA(1'b1),
// .TCENA(1'b0), .TCENA(1'b0),
// .TAA(5'b0), .TAA(5'b0),
// .TENB(1'b1), .TENB(1'b1),
// .TCENB(1'b0), .TCENB(1'b0),
// .TWENB(128'b0), .TWENB(128'b0),
// .TAB(5'b0), .TAB(5'b0),
// .TDB(128'b0), .TDB(128'b0),
// .RET1N(1'b1), .RET1N(1'b1),
// .SIA(2'b0), .SIA(2'b0),
// .SEA(1'b0), .SEA(1'b0),
// .DFTRAMBYP(1'b0), .DFTRAMBYP(1'b0),
// .SIB(2'b0), .SIB(2'b0),
// .SEB(1'b0), .SEB(1'b0),
// .COLLDISN(1'b1) .COLLDISN(1'b1)
// ); );
// /* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */
// /* verilator lint_off PINCONNECTEMPTY */ /* verilator lint_off PINCONNECTEMPTY */
// rf2_32x128_wm1 second_ram ( rf2_32x128_wm1 second_ram (
// .CENYA(), .CENYA(),
// .AYA(), .AYA(),
// .CENYB(), .CENYB(),
// .WENYB(), .WENYB(),
// .AYB(), .AYB(),
// .QA(out_b_reg_data), .QA(out_b_reg_data),
// .SOA(), .SOA(),
// .SOB(), .SOB(),
// .CLKA(clk), .CLKA(clk),
// .CENA(1'b0), .CENA(1'b0),
// .AA(VX_gpr_read.rs2), .AA(VX_gpr_read.rs2),
// .CLKB(clk), .CLKB(clk),
// .CENB(1'b0), .CENB(1'b0),
// .WENB(write_bit_mask), .WENB(write_bit_mask),
// .AB(VX_writeback_inter.rd), .AB(VX_writeback_inter.rd),
// .DB(VX_writeback_inter.write_data), .DB(VX_writeback_inter.write_data),
// .EMAA(3'b011), .EMAA(3'b011),
// .EMASA(1'b0), .EMASA(1'b0),
// .EMAB(3'b011), .EMAB(3'b011),
// .TENA(1'b1), .TENA(1'b1),
// .TCENA(1'b0), .TCENA(1'b0),
// .TAA(5'b0), .TAA(5'b0),
// .TENB(1'b1), .TENB(1'b1),
// .TCENB(1'b0), .TCENB(1'b0),
// .TWENB(128'b0), .TWENB(128'b0),
// .TAB(5'b0), .TAB(5'b0),
// .TDB(128'b0), .TDB(128'b0),
// .RET1N(1'b1), .RET1N(1'b1),
// .SIA(2'b0), .SIA(2'b0),
// .SEA(1'b0), .SEA(1'b0),
// .DFTRAMBYP(1'b0), .DFTRAMBYP(1'b0),
// .SIB(2'b0), .SIB(2'b0),
// .SEB(1'b0), .SEB(1'b0),
// .COLLDISN(1'b1) .COLLDISN(1'b1)
// ); );
// /* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */
endmodule endmodule

8
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 52683 # Dynamic Instructions: 15
# of total cycles: 52699 # of total cycles: 28
# of forwarding stalls: 0 # of forwarding stalls: 0
# of branch stalls: 0 # of branch stalls: 0
# CPI: 1.0003 # CPI: 1.86667
# time to simulate: 0 milliseconds # time to simulate: 6.95313e-310 milliseconds
# GRADE: Failed on test: 4294967295 # GRADE: Failed on test: 4294967295

2
rtl/simulate/tb_debug.h
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@@ -1 +1 @@
#define VCD_OFF #define VCD_OUTPUT

8
rtl/simulate/test_bench.h
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@@ -21,6 +21,13 @@
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#endif #endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
class Vortex class Vortex
{ {
public: public:
@@ -404,6 +411,7 @@ bool Vortex::simulate(std::string file_to_simulate)
counter = 0; counter = 0;
} }
++time_stamp;
++stats_total_cycles; ++stats_total_cycles;
} }