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cache refactoring - phase 3 - added dedicated pipeline stage for tag access

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Blaise Tine
2020-11-04 03:21:30 -08:00
parent cd8ce20bd6
commit 4c6a74fa87
11 changed files with 545 additions and 339 deletions
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hw/rtl/VX_alu_unit.v
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@@ -31,7 +31,7 @@ module VX_alu_unit #(
wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && !is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin