Merge branch 'master' of https://github.gatech.edu/casl/Vortex

driver/tests/dogfood/kernel.c

@@ -131,8 +131,9 @@ void kernel_fmadd(void* arg) {
 	for (uint32_t i = 0; i < count; ++i) {
 		float a = src0_ptr[offset+i];
 		float b = src1_ptr[offset+i];
-		float c = a * b + 0.5f;
+		float c = a - b;
-		dst_ptr[offset+i] = c;
+		float d = a * b + c;
+		dst_ptr[offset+i] = d;
 	}
 }
 
@@ -147,8 +148,9 @@ void kernel_fmsub(void* arg) {
 	for (uint32_t i = 0; i < count; ++i) {
 		float a = src0_ptr[offset+i];
 		float b = src1_ptr[offset+i];
-		float c = a * b - 0.5f;
+		float c = a - b;
-		dst_ptr[offset+i] = c;
+		float d = a * b - c;
+		dst_ptr[offset+i] = d;
 	}
 }
 
@@ -163,8 +165,9 @@ void kernel_fnmadd(void* arg) {
 	for (uint32_t i = 0; i < count; ++i) {
 		float a = src0_ptr[offset+i];
 		float b = src1_ptr[offset+i];
-		float c = -a * b - 0.5f;
+		float c = a - b;
-		dst_ptr[offset+i] = c;
+		float d =-a * b - c;
+		dst_ptr[offset+i] = d;
 	}
 }
 
@@ -179,8 +182,9 @@ void kernel_fnmsub(void* arg) {
 	for (uint32_t i = 0; i < count; ++i) {
 		float a = src0_ptr[offset+i];
 		float b = src1_ptr[offset+i];
-		float c = -a * b + 0.5f;
+		float c = a - b;
-		dst_ptr[offset+i] = c;
+		float d =-a * b + c;
+		dst_ptr[offset+i] = d;
 	}
 }
 
@@ -195,10 +199,11 @@ void kernel_fnmadd_madd(void* arg) {
 	for (uint32_t i = 0; i < count; ++i) {
 		float a = src0_ptr[offset+i];
 		float b = src1_ptr[offset+i];
-		float c =-a * b - 0.5f;
+		float c = a - b;
-		float d = a * b + 0.5f;
+		float d =-a * b - c;
-		float e = c + d;
+		float e = a * b + c;
-		dst_ptr[offset+i] = e;
+		float f = d + e;
+		dst_ptr[offset+i] = f;
 	}
 }
 

driver/tests/dogfood/testcases.h

@@ -19,7 +19,7 @@ inline bool almost_equal_eps(float a, float b, float eps = std::numeric_limits<f
   return fabs(a - b) <= tolerance;
 }
 
-inline bool almost_equal_ulp(float a, float b, int32_t ulp = 4) {
+inline bool almost_equal_ulp(float a, float b, int32_t ulp = 5) {
   Float_t fa{a}, fb{b};
   return std::abs(fa.i - fb.i) <= ulp;
 }
@@ -253,7 +253,8 @@ public:
     auto b = (float*)src2;
     auto c = (float*)dst;
     for (int i = 0; i < n; ++i) {
-      auto ref = a[i] * b[i] + 0.5f;
+      auto x = a[i] - b[i];
+      auto ref = a[i] * b[i] + x;
       if (!almost_equal(c[i], ref)) {
         std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl;
         ++errors;
@@ -281,7 +282,8 @@ public:
     auto b = (float*)src2;
     auto c = (float*)dst;
     for (int i = 0; i < n; ++i) {
-      auto ref = a[i] * b[i] - 0.5f;
+      auto x = a[i] - b[i];
+      auto ref = a[i] * b[i] - x;
       if (!almost_equal(c[i], ref)) {
         std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl;
         ++errors;
@@ -309,7 +311,8 @@ public:
     auto b = (float*)src2;
     auto c = (float*)dst;
     for (int i = 0; i < n; ++i) {
-      auto ref = -a[i] * b[i] - 0.5f;
+      auto x = a[i] - b[i];
+      auto ref = -a[i] * b[i] - x;
       if (!almost_equal(c[i], ref)) {
         std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl;
         ++errors;
@@ -337,7 +340,8 @@ public:
     auto b = (float*)src2;
     auto c = (float*)dst;
     for (int i = 0; i < n; ++i) {
-      auto ref = -a[i] * b[i] + 0.5f;
+      auto x = a[i] - b[i];
+      auto ref = -a[i] * b[i] + x;
       if (!almost_equal(c[i], ref)) {
         std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl;
         ++errors;
@@ -365,9 +369,10 @@ public:
     auto b = (float*)src2;
     auto c = (float*)dst;
     for (int i = 0; i < n; ++i) {
-      auto x = -a[i] * b[i] - 0.5f;
+      auto x = a[i] - b[i];
-      auto y =  a[i] * b[i] + 0.5f;
+      auto y = -a[i] * b[i] - x;
-      auto ref = x + y;
+      auto z =  a[i] * b[i] + x;
+      auto ref = y + z;
       if (!almost_equal(c[i], ref)) {
         std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl;
         ++errors;

hw/unit_tests/cache/cachesim.cpp

@@ -58,6 +58,7 @@ void CacheSim::reset() {
 }
 
 void CacheSim::step() {
+  std::cout << timestamp << ": [sim] step()" << std::endl;
   //toggle clock
   cache_->clk = 0;
   this->eval();
@@ -69,6 +70,7 @@ void CacheSim::step() {
   this->eval_reqs();
   this->eval_rsps();
   this->eval_dram_bus();
+  timestamp++;
 }
 
 void CacheSim::eval() {
@@ -80,14 +82,15 @@ void CacheSim::eval() {
 }
 
 void CacheSim::run(){
-#ifndef NDEBUG
+//#ifndef NDEBUG
-  std::cout << timestamp << ": [sim] run()" << std::endl;
+  
-#endif
+//#endif
   this->step();
 
   int valid = 300; 
   
   while (valid > -1) {
+
       this->step();
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
         valid--; 
@@ -251,12 +254,14 @@ void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
   rsp[1] = cache_->core_rsp_data[1];
   rsp[2] = cache_->core_rsp_data[2];
   rsp[3] = cache_->core_rsp_data[3];
+
   //std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
   //std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
   //std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
 }
 
 void CacheSim::get_core_req(){
+  std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
   char check = cache_->core_req_valid;
   std::cout << std::hex << "core_req_valid: " << check << std::endl;
   std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;

hw/unit_tests/cache/cachesim.h

@@ -52,6 +52,7 @@ public:
   void clear_req(); 
   void send_req(core_req_t *req);
   bool assert_equal(unsigned int* data, unsigned int tag);
+  //void time_analyisis 
 
   //display funcs
 

hw/unit_tests/cache/testbench.cpp

@@ -5,13 +5,8 @@
 
 #define VCD_OUTPUT 1
 
-int main(int argc, char **argv)
-{
-  //init
-  RAM ram;
-	CacheSim cachesim;
-  cachesim.attach_ram(&ram);
 
+int REQ_RSP(CacheSim *sim){ //verified
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
@@ -34,21 +29,186 @@ int main(int argc, char **argv)
   read->data = addr; 
   read->tag = 0xff;
   
-	// reset the device
+  // reset the device
-  cachesim.reset();
+  sim->reset();
 
   //queue reqs
-  cachesim.send_req(write);
+  sim->send_req(write);
-  cachesim.send_req(read);
+  sim->send_req(read);
 
-  cachesim.run(); 
+  sim->run();
 
-  bool check = cachesim.assert_equal(data, write->tag);
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int HIT_1(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0x11;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0x22;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int MISS_1(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+int FLUSH(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+
+int BACK_PRESSURE(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  for (int i = 0; i < 10; i++){
+    sim->send_req(write);
+  }
+  sim->send_req(read); 
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+
+int main(int argc, char **argv)
+{
+  //init
+  RAM ram;
+	CacheSim cachesim;
+  cachesim.attach_ram(&ram);
+  int check = HIT_1(&cachesim);
   if(check){
     std::cout << "PASSED" << std::endl;
   } else {
     std::cout << "FAILED" << std::endl;
   }
   
+
+
 	return 0;
 }