From 4bd5ee26732ca9c13854dfa1731e5fb00cd6c28f Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Mon, 26 Oct 2020 12:59:58 -0400
Subject: [PATCH] fixed rtlsim regression

---
 driver/rtlsim/Makefile    |  2 +-
 hw/simulate/simulator.cpp | 14 +++++++-------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile
index 4db05ba8..1a66b335 100644
--- a/driver/rtlsim/Makefile
+++ b/driver/rtlsim/Makefile
@@ -55,7 +55,7 @@ VL_FLAGS += verilator.vlt
 
 # Debugigng
 ifdef DEBUG
-	VL_FLAGS += -DVCD_OUTPUT --assert --trace $(DBG_FLAGS)
+	VL_FLAGS += -DVCD_OUTPUT --assert --trace-fst --trace-threads 1 $(DBG_FLAGS)
 	CFLAGS   += -DVCD_OUTPUT $(DBG_FLAGS)
 else    
 	VL_FLAGS += -DNDEBUG
diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp
index 2698cc74..4f6403e7 100644
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -96,15 +96,15 @@ void Simulator::reset() {
 }
 
 void Simulator::step() {
-  this->eval_dram_bus();
-  this->eval_io_bus();
-  this->eval_csr_bus();
-  this->eval_snp_bus();
-
   vortex_->clk = 0;
   this->eval();
   vortex_->clk = 1;
   this->eval();
+  
+  this->eval_dram_bus();
+  this->eval_io_bus();
+  this->eval_csr_bus();
+  this->eval_snp_bus();
 }
 
 void Simulator::eval() {
@@ -216,7 +216,7 @@ void Simulator::eval_snp_bus() {
     #endif
     }
     if (vortex_->snp_req_valid && vortex_->snp_req_ready) {            
-      if (snp_req_size_) {        
+      if (snp_req_size_ != 0) {        
         vortex_->snp_req_addr += 1;
         vortex_->snp_req_tag  += 1;
         --snp_req_size_;
@@ -289,7 +289,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
   vortex_->snp_req_valid = 1;
   vortex_->snp_rsp_ready = 1;  
 
-  snp_req_size_   = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE; 
+  snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE; 
   --snp_req_size_;
   pending_snp_reqs_ = 1;