fixed reset fan-out

driver/opae/vlsim/opae_sim.cpp

@@ -8,7 +8,7 @@
 #define CCI_RQ_SIZE 16
 #define CCI_WQ_SIZE 16
 
-#define RESET_DELAY 1
+#define RESET_DELAY 2
 
 #define ENABLE_DRAM_STALLS
 #define DRAM_LATENCY 24
@@ -38,8 +38,10 @@ opae_sim::opae_sim() {
   trace_->open("trace.vcd");
 #endif
 
+  // reset the device
   this->reset();
 
+  // launch execution thread
   stop_ = false;
   future_ = std::async(std::launch::async, [&]{                   
       while (!stop_) {
@@ -140,7 +142,15 @@ void opae_sim::reset() {
 
   vortex_afu_->reset = 0;
 
-  reset_time_ = timestamp; 
+  for (int i = 0; i < RESET_DELAY; ++i) {
+    vortex_afu_->clk = 0;
+    this->eval();
+    vortex_afu_->clk = 1;
+    this->eval();
+  }  
+  
+  // Turn on assertion after reset
+  Verilated::assertOn(true);
 }
 
 void opae_sim::step() {
@@ -154,11 +164,6 @@ void opae_sim::step() {
   vortex_afu_->clk = 1;
   this->eval();
 
-  if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
-    // Turn on assertion after reset
-    Verilated::assertOn(true);
-  }
-
 #ifndef NDEBUG
   fflush(stdout);
 #endif

driver/opae/vlsim/opae_sim.h

@@ -85,8 +85,6 @@ private:
 
   std::mutex mutex_;
 
-  uint64_t reset_time_;
-
   RAM ram_;
   Vvortex_afu_shim *vortex_afu_;
 #ifdef VCD_OUTPUT

driver/tests/dogfood/Makefile

@@ -8,7 +8,7 @@ VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++
 VX_DP  = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump
 VX_CP  = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy
 
-VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld -nostartfiles -Wl,--gc-sections
+VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld -nostartfiles -Wl,--gc-sections,-Map,kernel.map
 VX_CFLAGS += -I$(VORTEX_RT_PATH)/include
 
 VX_LDFLAGS += $(VORTEX_RT_PATH)/libvortexrt.a
@@ -28,7 +28,7 @@ SRCS = dogfood.cpp
 all: $(PROJECT) kernel.bin kernel.dump
  
 kernel.dump: kernel.elf
-	$(VX_DP) -D kernel.elf > kernel.dump
+	$(VX_DP) -d -r -t kernel.elf > kernel.dump
 
 kernel.bin: kernel.elf
 	$(VX_CP) -O binary kernel.elf kernel.bin

hw/rtl/VX_cluster.v

@@ -68,10 +68,16 @@ module VX_cluster #(
     wire [`NUM_CORES-1:0]                        per_core_ebreak;
 
     for (genvar i = 0; i < `NUM_CORES; i++) begin
-
+        
-        reg core_reset;
+        wire core_reset;
-        always @(posedge clk) begin
+        if (`NUM_CORES > 1) begin
-            core_reset <= reset;
+            reg core_reset_r;
+            always @(posedge clk) begin
+                core_reset_r <= reset;
+            end
+            assign core_reset = core_reset_r;
+        end else begin
+            assign core_reset = reset;
         end
 
         VX_core #(
@@ -158,7 +164,7 @@ module VX_cluster #(
         VX_cache #(
             .CACHE_ID           (`L2CACHE_ID),
             .CACHE_SIZE         (`L2CACHE_SIZE),
-            .CACHE_LINE_SIZE     (`L2CACHE_LINE_SIZE),
+            .CACHE_LINE_SIZE    (`L2CACHE_LINE_SIZE),
             .NUM_BANKS          (`L2NUM_BANKS),
             .WORD_SIZE          (`L2WORD_SIZE),
             .NUM_REQS           (`NUM_CORES),

hw/rtl/VX_lsu_unit.v

@@ -77,7 +77,8 @@ module VX_lsu_unit #(
 
     VX_pipe_register #(
         .DATAW  (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
-        .RESETW (1)
+        .RESETW (1),
+        .DEPTH  (0)
     ) req_pipe_reg (
         .clk      (clk),
         .reset    (reset),

hw/rtl/Vortex.v

@@ -39,6 +39,7 @@ module Vortex (
     output wire                             busy, 
     output wire                             ebreak
 );
+
     wire [`NUM_CLUSTERS-1:0]                         per_cluster_dram_req_valid;
     wire [`NUM_CLUSTERS-1:0]                         per_cluster_dram_req_rw;
     wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen;
@@ -69,13 +70,25 @@ module Vortex (
     wire [`NC_BITS-1:0] csr_core_id = `NC_BITS'(csr_req_coreid);
 
     for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
+
+        wire cluster_reset;
+        if (`NUM_CLUSTERS > 1) begin
+            reg cluster_reset_r;
+            always @(posedge clk) begin
+                cluster_reset_r <= reset;
+            end
+            assign cluster_reset = cluster_reset_r;
+        end else begin
+            assign cluster_reset = reset;
+        end
+
         VX_cluster #(
             .CLUSTER_ID(i)
         ) cluster (
             `SCOPE_BIND_Vortex_cluster(i)
 
             .clk            (clk),
-            .reset          (reset),
+            .reset          (cluster_reset),
 
             .dram_req_valid (per_cluster_dram_req_valid [i]),
             .dram_req_rw    (per_cluster_dram_req_rw    [i]),

hw/simulate/simulator.cpp

@@ -3,7 +3,7 @@
 #include <fstream>
 #include <iomanip>
 
-#define RESET_DELAY 1
+#define RESET_DELAY 2
 
 #define ENABLE_DRAM_STALLS
 #define DRAM_LATENCY 24
@@ -83,7 +83,15 @@ void Simulator::reset() {
 
   vortex_->reset = 0;
 
-  reset_time_ = timestamp;
+  for (int i = 0; i < RESET_DELAY; ++i) {
+    vortex_->clk = 0;
+    this->eval();
+    vortex_->clk = 1;
+    this->eval();
+  }  
+  
+  // Turn on assertion after reset
+  Verilated::assertOn(true);
 }
 
 void Simulator::step() {
@@ -91,7 +99,7 @@ void Simulator::step() {
   vortex_->clk = 0;
   this->eval();
 
-  dram_rsp_ready_   = vortex_->dram_rsp_ready;
+  dram_rsp_ready_ = vortex_->dram_rsp_ready;
   csr_req_ready_ = vortex_->csr_req_ready;
   
   vortex_->clk = 1;
@@ -100,11 +108,6 @@ void Simulator::step() {
   this->eval_dram_bus();
   this->eval_io_bus();
   this->eval_csr_bus();
-  
-  if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
-    // Turn on assertion after reset
-    Verilated::assertOn(true);
-  }
 
 #ifndef NDEBUG
   fflush(stdout);

hw/simulate/simulator.h

@@ -69,8 +69,6 @@ private:
   bool csr_req_active_;
   uint32_t* csr_rsp_value_;
 
-  uint64_t reset_time_;
-
   RAM *ram_;
   VVortex *vortex_;
 #ifdef VCD_OUTPUT