fixed reset fan-out
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@@ -3,7 +3,7 @@
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#include <fstream>
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#include <iomanip>
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#define RESET_DELAY 1
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#define RESET_DELAY 2
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 24
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@@ -83,7 +83,15 @@ void Simulator::reset() {
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vortex_->reset = 0;
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reset_time_ = timestamp;
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for (int i = 0; i < RESET_DELAY; ++i) {
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vortex_->clk = 0;
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this->eval();
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vortex_->clk = 1;
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this->eval();
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}
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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void Simulator::step() {
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@@ -91,7 +99,7 @@ void Simulator::step() {
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vortex_->clk = 0;
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this->eval();
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dram_rsp_ready_ = vortex_->dram_rsp_ready;
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dram_rsp_ready_ = vortex_->dram_rsp_ready;
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csr_req_ready_ = vortex_->csr_req_ready;
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vortex_->clk = 1;
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@@ -100,11 +108,6 @@ void Simulator::step() {
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this->eval_dram_bus();
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this->eval_io_bus();
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this->eval_csr_bus();
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if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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#ifndef NDEBUG
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fflush(stdout);
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