fixed reset fan-out
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@@ -8,7 +8,7 @@
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#define CCI_RQ_SIZE 16
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#define CCI_WQ_SIZE 16
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#define RESET_DELAY 1
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#define RESET_DELAY 2
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 24
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@@ -38,8 +38,10 @@ opae_sim::opae_sim() {
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trace_->open("trace.vcd");
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#endif
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// reset the device
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this->reset();
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// launch execution thread
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stop_ = false;
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future_ = std::async(std::launch::async, [&]{
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while (!stop_) {
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@@ -140,7 +142,15 @@ void opae_sim::reset() {
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vortex_afu_->reset = 0;
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reset_time_ = timestamp;
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for (int i = 0; i < RESET_DELAY; ++i) {
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vortex_afu_->clk = 0;
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this->eval();
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vortex_afu_->clk = 1;
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this->eval();
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}
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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void opae_sim::step() {
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@@ -154,11 +164,6 @@ void opae_sim::step() {
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vortex_afu_->clk = 1;
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this->eval();
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if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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#ifndef NDEBUG
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fflush(stdout);
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#endif
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