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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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87
hw/rtl/libs/VX_stream_arbiter.v
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@@ -1,11 +1,10 @@
`include "VX_platform.vh"
module VX_stream_arbiter #(
parameter NUM_REQS = 1,
parameter DATAW = 1,
parameter TYPE = "R",
parameter IN_BUFFER = 0,
parameter OUT_BUFFER = 0
parameter NUM_REQS = 1,
parameter DATAW = 1,
parameter TYPE = "R",
parameter BUFFERED = 0
) (
input wire clk,
input wire reset,
@@ -22,27 +21,6 @@ module VX_stream_arbiter #(
localparam LOG_NUM_REQS = $clog2(NUM_REQS);
if (NUM_REQS > 1) begin
wire [NUM_REQS-1:0] valid_in_qual;
wire [NUM_REQS-1:0][DATAW-1:0] data_in_qual;
wire [NUM_REQS-1:0] ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!IN_BUFFER)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in (valid_in[i]),
.data_in (data_in[i]),
.ready_in (ready_in[i]),
.valid_out (valid_in_qual[i]),
.data_out (data_in_qual[i]),
.ready_out (ready_in_qual[i])
);
end
wire sel_enable;
wire sel_valid;
wire [LOG_NUM_REQS-1:0] sel_idx;
@@ -56,7 +34,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
@@ -71,7 +49,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
@@ -86,7 +64,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
@@ -101,47 +79,36 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
);
end
end
if (OUT_BUFFER) begin
wire ready_out_unqual;
wire stall = ~ready_out && valid_out;
assign sel_enable = ~stall;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (sel_valid),
.data_in (data_in[sel_idx]),
.ready_in (ready_out_unqual),
.valid_out (valid_out),
.data_out (data_out),
.ready_out (ready_out)
);
VX_generic_register #(
.N(1 + DATAW),
.R(1)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({sel_valid, data_in_qual[sel_idx]}),
.data_out ({valid_out, data_out})
);
assign sel_enable = ready_out_unqual;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in_qual[i] = sel_1hot[i] && ~stall;
end
end else begin
assign sel_enable = ready_out;
assign valid_out = sel_valid;
assign data_out = data_in_qual[sel_idx];
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in_qual[i] = sel_1hot[i] && ready_out;
end
end
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ready_out_unqual;
end
end else begin