performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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@@ -143,7 +143,7 @@ module VX_scope #(
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end
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if (stop
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|| (waddr >= waddr_end)) begin
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|| (waddr == waddr_end)) begin
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waddr <= waddr; // keep last address
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recording <= 0;
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data_valid <= 1;
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