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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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4
hw/rtl/interfaces/VX_decode_if.v
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@@ -6,7 +6,6 @@
interface VX_decode_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -21,8 +20,7 @@ interface VX_decode_if ();
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [`NUM_REGS-1:0] used_regs;
wire [`NUM_REGS-1:0] used_regs;
wire ready;
endinterface