performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/rtl/interfaces/VX_csr_io_req_if.v
+++ b/hw/rtl/interfaces/VX_csr_io_req_if.v
@@ -5,12 +5,10 @@

 interface VX_csr_io_req_if ();

-    wire                      valid;
-    
+    wire                      valid;    
    wire [`CSR_ADDR_BITS-1:0] addr;
    wire                      rw;
    wire [31:0]               data;
-
    wire                      ready;
    
 endinterface