performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

hw/rtl/interfaces/VX_cache_dram_req_if.v

@@ -9,14 +9,12 @@ interface VX_cache_dram_req_if #(
     parameter DRAM_TAG_WIDTH  = 1
 ) ();
 
-    wire                           valid;
-    
+    wire                           valid;    
     wire                           rw;    
     wire [(DRAM_LINE_WIDTH/8)-1:0] byteen;
     wire [DRAM_ADDR_WIDTH-1:0]     addr;
     wire [DRAM_LINE_WIDTH-1:0]     data;  
-    wire [DRAM_TAG_WIDTH-1:0]      tag;   
-
+    wire [DRAM_TAG_WIDTH-1:0]      tag;  
     wire                           ready;
 
 endinterface