performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/rtl/cache/VX_data_store.v
+++ b/hw/rtl/cache/VX_data_store.v
@@ -46,7 +46,6 @@ module VX_data_store #(
        .DATAW(BANK_LINE_SIZE * 8),
        .SIZE(`BANK_LINE_COUNT),
        .BYTEENW(BANK_LINE_SIZE),
-        .BUFFERED(0),
        .RWCHECK(1)
    ) data (
        .clk(clk),