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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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12
hw/rtl/cache/VX_cache.v vendored
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@@ -378,9 +378,9 @@ module VX_cache #(
end
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.BUFFERED (1)
) dram_req_arb (
.clk (clk),
.reset (reset),
@@ -408,9 +408,9 @@ module VX_cache #(
if (FLUSH_ENABLE) begin
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.BUFFERED (1)
) snp_rsp_arb (
.clk (clk),
.reset (reset),