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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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338
hw/rtl/cache/VX_bank.v vendored
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@@ -111,36 +111,24 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
/* verilator lint_off UNUSED */
wire[31:0] debug_pc_st0;
wire[`NR_BITS-1:0] debug_rd_st0;
wire[`NW_BITS-1:0] debug_wid_st0;
wire debug_rw_st0;
wire[WORD_SIZE-1:0] debug_byteen_st0;
wire[`REQS_BITS-1:0] debug_tid_st0;
wire [31:0] debug_pc_st0;
wire [`NR_BITS-1:0] debug_rd_st0;
wire [`NW_BITS-1:0] debug_wid_st0;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0;
wire[31:0] debug_pc_st1;
wire[`NR_BITS-1:0] debug_rd_st1;
wire[`NW_BITS-1:0] debug_wid_st1;
wire debug_rw_st1;
wire[WORD_SIZE-1:0] debug_byteen_st1;
wire[`REQS_BITS-1:0] debug_tid_st1;
wire [31:0] debug_pc_st1;
wire [`NR_BITS-1:0] debug_rd_st1;
wire [`NW_BITS-1:0] debug_wid_st1;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1;
wire[31:0] debug_pc_st2;
wire[`NR_BITS-1:0] debug_rd_st2;
wire[`NW_BITS-1:0] debug_wid_st2;
wire debug_rw_st2;
wire[WORD_SIZE-1:0] debug_byteen_st2;
wire[`REQS_BITS-1:0] debug_tid_st2;
wire [31:0] debug_pc_st2;
wire [`NR_BITS-1:0] debug_rd_st2;
wire [`NW_BITS-1:0] debug_wid_st2;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
wire[31:0] debug_pc_st3;
wire[`NR_BITS-1:0] debug_rd_st3;
wire[`NW_BITS-1:0] debug_wid_st3;
wire debug_rw_st3;
wire[WORD_SIZE-1:0] debug_byteen_st3;
wire[`REQS_BITS-1:0] debug_tid_st3;
wire [31:0] debug_pc_st3;
wire [`NR_BITS-1:0] debug_rd_st3;
wire [`NW_BITS-1:0] debug_wid_st3;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st3;
/* verilator lint_on UNUSED */
`endif
@@ -159,9 +147,10 @@ module VX_bank #(
wire sreq_push = snp_req_valid && snp_req_ready;
VX_generic_queue #(
.DATAW(`LINE_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE(SREQ_SIZE),
.BUFFERED(1)
.DATAW (`LINE_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE (SREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) snp_req_queue (
.clk (clk),
.reset (reset),
@@ -200,9 +189,10 @@ module VX_bank #(
assign dram_rsp_ready = !drsq_full;
VX_generic_queue #(
.DATAW(`LINE_ADDR_WIDTH + $bits(dram_rsp_data)),
.SIZE(DRSQ_SIZE),
.BUFFERED(1)
.DATAW (`LINE_ADDR_WIDTH + $bits(dram_rsp_data)),
.SIZE (DRSQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) dram_rsp_queue (
.clk (clk),
.reset (reset),
@@ -246,30 +236,30 @@ module VX_bank #(
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) core_req_queue (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Enqueue
.push (creq_push),
.tag_in (core_req_tag),
.valids_in (core_req_valid),
.rw_in (core_req_rw),
.byteen_in (core_req_byteen),
.addr_in (core_req_addr),
.writedata_in (core_req_data),
.push (creq_push),
.tag_in (core_req_tag),
.valids_in (core_req_valid),
.rw_in (core_req_rw),
.byteen_in (core_req_byteen),
.addr_in (core_req_addr),
.wdata_in (core_req_data),
// Dequeue
.pop (creq_pop),
.tag_out (creq_tag_st0),
.tid_out (creq_tid_st0),
.rw_out (creq_rw_st0),
.byteen_out (creq_byteen_st0),
.addr_out (creq_addr_st0),
.writedata_out (creq_writeword_st0),
.pop (creq_pop),
.tag_out (creq_tag_st0),
.tid_out (creq_tid_st0),
.rw_out (creq_rw_st0),
.byteen_out (creq_byteen_st0),
.addr_out (creq_addr_st0),
.wdata_out (creq_writeword_st0),
// States
.empty (creq_empty),
.full (creq_full)
.empty (creq_empty),
.full (creq_full)
);
reg [$clog2(MSHR_SIZE+1)-1:0] mshr_pending_size;
@@ -277,7 +267,7 @@ module VX_bank #(
reg mshr_going_full;
wire mshr_pop;
wire mshr_valid_st0;
wire[`REQS_BITS-1:0] mshr_tid_st0;
wire [`REQS_BITS-1:0] mshr_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mshr_addr_st0;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] mshr_wsel_st0;
wire [`WORD_WIDTH-1:0] mshr_writeword_st0;
@@ -286,6 +276,7 @@ module VX_bank #(
wire [WORD_SIZE-1:0] mshr_byteen_st0;
wire mshr_is_snp_st0;
wire mshr_snp_inv_st0;
wire mshr_pending_hazard_unqual_st0;
wire is_fill_st0;
wire is_mshr_st0;
@@ -295,9 +286,11 @@ module VX_bank #(
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st0;
wire [`WORD_WIDTH-1:0] writeword_st0;
wire [`BANK_LINE_WIDTH-1:0] writedata_st0;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st0;
wire snp_inv_st0;
wire mshr_pending_hazard_unqual_st0;
wire [`REQ_TAG_WIDTH-1:0] tag_st0;
wire mem_rw_st0;
wire [WORD_SIZE-1:0] byteen_st0;
wire [`REQS_BITS-1:0] req_tid_st0;
wire is_fill_st1;
wire is_mshr_st1;
@@ -306,32 +299,26 @@ module VX_bank #(
wire [`LINE_ADDR_WIDTH-1:0] addr_st1;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1;
wire [`WORD_WIDTH-1:0] writeword_st1;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1;
wire [`BANK_LINE_WIDTH-1:0] writedata_st1;
wire snp_inv_st1;
wire [`TAG_SELECT_BITS-1:0] readtag_st1;
wire miss_st1;
wire force_miss_st1;
wire dirty_st1;
wire [WORD_SIZE-1:0] mem_byteen_st1;
wire writeen_st1;
wire mem_rw_st1;
`DEBUG_BEGIN
wire [`REQ_TAG_WIDTH-1:0] tag_st1;
wire [`REQS_BITS-1:0] tid_st1;
`DEBUG_END
wire mem_rw_st1;
wire [WORD_SIZE-1:0] byteen_st1;
wire [`REQS_BITS-1:0] req_tid_st1;
wire valid_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
wire [`BANK_LINE_WIDTH-1:0] writedata_st2;
wire [WORD_SIZE-1:0] mem_byteen_st2;
wire dirty_st2;
wire [BANK_LINE_SIZE-1:0] dirtyb_st2;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2;
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
wire is_fill_st2;
wire is_snp_st2;
@@ -342,15 +329,22 @@ module VX_bank #(
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire writeen_st2;
wire core_req_hit_st2;
wire incoming_fill_st2;
wire [`REQ_TAG_WIDTH-1:0] tag_st2;
wire mem_rw_st2;
wire [WORD_SIZE-1:0] byteen_st2;
wire [`REQS_BITS-1:0] req_tid_st2;
wire valid_st3;
wire is_mshr_st3;
wire miss_st3;
wire force_miss_st3;
wire [`LINE_ADDR_WIDTH-1:0] addr_st3;
wire core_req_hit_st1;
wire [`REQ_TAG_WIDTH-1:0] tag_st3;
wire mem_rw_st3;
wire [WORD_SIZE-1:0] byteen_st3;
wire [`REQS_BITS-1:0] req_tid_st3;
wire mshr_push_stall;
wire crsq_push_stall;
wire dreq_push_stall;
@@ -360,7 +354,7 @@ module VX_bank #(
wire is_mshr_miss_st2 = valid_st2 && is_mshr_st2 && (miss_st2 || force_miss_st2);
wire is_mshr_miss_st3 = valid_st3 && is_mshr_st3 && (miss_st3 || force_miss_st3);
wire creq_commit = valid_st1 && core_req_hit_st1 && !pipeline_stall;
wire creq_commit = valid_st2 && core_req_hit_st2 && !pipeline_stall;
// determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid_st0;
@@ -383,7 +377,7 @@ module VX_bank #(
mshr_going_full <= 0;
end else begin
mshr_pending_size <= mshr_pending_size_n;
mshr_going_full <= (mshr_pending_size_n == MSHR_SIZE);
mshr_going_full <= (mshr_pending_size_n == MSHR_SIZE);
end
end
@@ -409,10 +403,25 @@ module VX_bank #(
assign writedata_st0 = drsq_filldata_st0;
assign inst_meta_st0 = mshr_pop_unqual ? {`REQ_TAG_WIDTH'(mshr_tag_st0), mshr_rw_st0, mshr_byteen_st0, mshr_tid_st0} :
creq_pop_unqual ? {`REQ_TAG_WIDTH'(creq_tag_st0), creq_rw_st0, creq_byteen_st0, creq_tid_st0} :
sreq_pop_unqual ? {`REQ_TAG_WIDTH'(sreq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} :
0;
assign tag_st0 = mshr_pop_unqual ? `REQ_TAG_WIDTH'(mshr_tag_st0) :
creq_pop_unqual ? `REQ_TAG_WIDTH'(creq_tag_st0) :
sreq_pop_unqual ? `REQ_TAG_WIDTH'(sreq_tag_st0) :
0;
assign mem_rw_st0 = mshr_pop_unqual ? mshr_rw_st0 :
creq_pop_unqual ? creq_rw_st0 :
sreq_pop_unqual ? 1'b0 :
0;
assign byteen_st0 = mshr_pop_unqual ? mshr_byteen_st0 :
creq_pop_unqual ? creq_byteen_st0 :
sreq_pop_unqual ? WORD_SIZE'(0) :
0;
assign req_tid_st0 = mshr_pop_unqual ? mshr_tid_st0 :
creq_pop_unqual ? creq_tid_st0 :
sreq_pop_unqual ? `REQS_BITS'(0) :
0;
assign is_snp_st0 = mshr_pop_unqual ? mshr_is_snp_st0 :
sreq_pop_unqual ? 1 :
@@ -428,9 +437,9 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = inst_meta_st0;
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0} = tag_st0;
end else begin
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = 0;
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0} = 0;
end
`endif
@@ -443,27 +452,25 @@ if (DRAM_ENABLE) begin
|| (valid_st3 && (miss_st3 || force_miss_st3) && (addr_st3 == addr_st0));
VX_generic_register #(
.N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH),
.N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg0 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st0, is_mshr_st0, is_snp_st0, snp_inv_st0, mshr_pending_hazard_st0, addr_st0, wsel_st0, writeword_st0, inst_meta_st0, is_fill_st0, writedata_st0}),
.data_out ({valid_st1, is_mshr_st1, is_snp_st1, snp_inv_st1, mshr_pending_hazard_st1, addr_st1, wsel_st1, writeword_st1, inst_meta_st1, is_fill_st1, writedata_st1})
.data_in ({valid_st0, is_mshr_st0, is_snp_st0, snp_inv_st0, mshr_pending_hazard_st0, addr_st0, wsel_st0, writeword_st0, is_fill_st0, writedata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}),
.data_out ({valid_st1, is_mshr_st1, is_snp_st1, snp_inv_st1, mshr_pending_hazard_st1, addr_st1, wsel_st1, writeword_st1, is_fill_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1})
);
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1;
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1} = tag_st1;
end else begin
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = 0;
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1} = 0;
end
`endif
assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1;
// force miss to ensure commit order when a new request has pending previous requests to same block
// also force a miss for msrq requests when previous requests got a miss
wire st2_pending_hazard_st1 = valid_st2 && (miss_st2 || force_miss_st2) && (addr_st2 == addr_st1);
@@ -511,20 +518,22 @@ if (DRAM_ENABLE) begin
.writeen_out (writeen_st1)
);
assign core_req_hit_st1 = !is_fill_st1 && !is_snp_st1 && !miss_st1 && !force_miss_st1;
assign misses = miss_st1;
wire core_req_hit_st1 = !is_fill_st1 && !is_snp_st1 && !miss_st1 && !force_miss_st1;
wire incoming_fill_st1 = !drsq_empty && (addr_st1 == drsq_addr_st0);
VX_generic_register #(
.N(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + WORD_SIZE + `REQ_INST_META_WIDTH),
.N(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st1, core_req_hit_st1, is_mshr_st1, writeen_st1, force_miss_st1, dirty_st1, is_snp_st1, snp_inv_st1, is_fill_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, writedata_st1, mem_byteen_st1, inst_meta_st1}),
.data_out ({valid_st2, core_req_hit_st2, is_mshr_st2, writeen_st2, force_miss_st2, dirty_st2, is_snp_st2, snp_inv_st2, is_fill_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, writedata_st2, mem_byteen_st2, inst_meta_st2})
.data_in ({valid_st1, incoming_fill_st1, core_req_hit_st1, is_mshr_st1, writeen_st1, force_miss_st1, dirty_st1, is_snp_st1, snp_inv_st1, is_fill_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}),
.data_out ({valid_st2, incoming_fill_st2, core_req_hit_st2, is_mshr_st2, writeen_st2, force_miss_st2, dirty_st2, is_snp_st2, snp_inv_st2, is_fill_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, writedata_st2, mem_rw_st2, byteen_st2, req_tid_st2, tag_st2})
);
end else begin
@@ -532,9 +541,7 @@ end else begin
`UNUSED_VAR (mshr_pending_hazard_unqual_st0)
`UNUSED_VAR (drsq_push)
`UNUSED_VAR (addr_st0)
assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1;
assign is_fill_st1 = is_fill_st0;
assign is_mshr_st1 = is_mshr_st0;
assign is_snp_st1 = is_snp_st0;
@@ -542,14 +549,17 @@ end else begin
assign wsel_st1 = wsel_st0;
assign writeword_st1= writeword_st0;
assign writedata_st1= writedata_st0;
assign inst_meta_st1= inst_meta_st0;
assign snp_inv_st1 = snp_inv_st0;
assign addr_st1 = creq_addr_st0[`LINE_SELECT_ADDR_RNG];
assign dirty_st1 = 0;
assign readtag_st1 = 0;
assign miss_st1 = 0;
assign writeen_st1 = valid_st1 && mem_rw_st1;
assign writeen_st1 = mem_rw_st1;
assign force_miss_st1 = 0;
assign tag_st1 = tag_st0;
assign mem_rw_st1 = mem_rw_st0;
assign byteen_st1 = byteen_st0;
assign req_tid_st1 = req_tid_st0;
assign is_fill_st2 = is_fill_st1;
assign is_mshr_st2 = is_mshr_st1;
@@ -558,20 +568,19 @@ end else begin
assign wsel_st2 = wsel_st1;
assign writeword_st2= writeword_st1;
assign writedata_st2= writedata_st1;
assign inst_meta_st2= inst_meta_st1;
assign snp_inv_st2 = snp_inv_st1;
assign addr_st2 = addr_st1;
assign dirty_st2 = dirty_st1;
assign mem_byteen_st2 = mem_byteen_st1;
assign readtag_st2 = readtag_st1;
assign miss_st2 = miss_st1;
assign writeen_st2 = writeen_st1;
assign force_miss_st2 = force_miss_st1;
assign tag_st2 = tag_st1;
assign mem_rw_st2 = mem_rw_st1;
assign byteen_st2 = byteen_st1;
assign req_tid_st2 = req_tid_st1;
assign core_req_hit_st1 = 0;
assign core_req_hit_st2 = 0;
assign send_dwb_req_st2 = 0;
assign do_writeback_st2 = 0;
assign core_req_hit_st2 = 1;
assign incoming_fill_st2 = 0;
assign misses = 0;
@@ -579,9 +588,9 @@ end
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2;
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2} = tag_st2;
end else begin
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = 0;
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2} = 0;
end
`endif
@@ -613,7 +622,7 @@ end
.writeen_in (writeen_st2),
.is_fill_in (is_fill_st2),
.wordsel_in (wsel_st2),
.byteen_in (mem_byteen_st2),
.byteen_in (byteen_st2),
.writeword_in (writeword_st2),
.writedata_in (writedata_st2),
@@ -628,62 +637,58 @@ end
wire [`WORD_WIDTH-1:0] readword_st3;
wire [`BANK_LINE_WIDTH-1:0] readdata_st3;
wire [BANK_LINE_SIZE-1:0] dirtyb_st3;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st3;
wire [`TAG_SELECT_BITS-1:0] readtag_st3;
wire is_snp_st3;
wire snp_inv_st3;
wire core_req_hit_st3;
wire send_dwb_req_st3;
wire do_writeback_st3;
wire incoming_fill_st3;
wire mshr_push_st3;
wire crsq_push_st3;
wire dreq_push_st3;
wire srsq_push_st3;
// check if a matching fill request is comming
wire incoming_fill_dfp_st2 = drsq_push && (addr_st2 == dram_rsp_addr);
wire incoming_fill_st0_st2 = !drsq_empty && (addr_st2 == drsq_addr_st0);
wire incoming_fill_st1_st2 = is_fill_st1 && (addr_st2 == addr_st1);
wire incoming_fill_st2 = incoming_fill_dfp_st2
|| incoming_fill_st0_st2
|| incoming_fill_st1_st2;
wire incoming_fill_qual_st2 = (!drsq_empty && (addr_st2 == drsq_addr_st0)) || incoming_fill_st2;
wire do_fill_req_st2 = miss_st2
&& (!force_miss_st2
|| (is_mshr_st2 && addr_st2 != addr_st3))
&& !incoming_fill_qual_st2;
wire send_fill_req_st2 = miss_st2
&& (!force_miss_st2
|| (is_mshr_st2 && addr_st2 != addr_st3))
&& !incoming_fill_st2;
wire do_writeback_st2 = dirty_st2
&& (is_fill_st2
|| (!force_miss_st2 && is_snp_st2));
wire do_writeback_st2 = dirty_st2
&& (is_fill_st2
|| (!force_miss_st2 && is_snp_st2));
wire mshr_push_st2 = miss_st2 || force_miss_st2;
wire send_dwb_req_st2 = send_fill_req_st2 || do_writeback_st2;
wire crsq_push_st2 = core_req_hit_st2 && !mem_rw_st2;
wire dreq_push_st2 = do_fill_req_st2 || do_writeback_st2;
wire srsq_push_st2 = is_snp_st2 && !force_miss_st2;
VX_generic_register #(
.N(1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH),
.N(1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + 1 + WORD_SIZE + `WORD_WIDTH + `BANK_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st2, core_req_hit_st2, send_dwb_req_st2, do_writeback_st2, incoming_fill_st2, force_miss_st2, is_mshr_st2, is_snp_st2, snp_inv_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirtyb_st2, inst_meta_st2}),
.data_out ({valid_st3, core_req_hit_st3, send_dwb_req_st3, do_writeback_st3, incoming_fill_st3, force_miss_st3, is_mshr_st3, is_snp_st3, snp_inv_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirtyb_st3, inst_meta_st3})
.data_in ({valid_st2, mshr_push_st2, crsq_push_st2, dreq_push_st2, srsq_push_st2, do_writeback_st2, incoming_fill_qual_st2, force_miss_st2, is_mshr_st2, is_snp_st2, snp_inv_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, dirtyb_st2, mem_rw_st2, byteen_st2, readword_st2, readdata_st2, req_tid_st2, tag_st2}),
.data_out ({valid_st3, mshr_push_st3, crsq_push_st3, dreq_push_st3, srsq_push_st3, do_writeback_st3, incoming_fill_st3, force_miss_st3, is_mshr_st3, is_snp_st3, snp_inv_st3, addr_st3, wsel_st3, writeword_st3, readtag_st3, miss_st3, dirtyb_st3, mem_rw_st3, byteen_st3, readword_st3, readdata_st3, req_tid_st3, tag_st3})
);
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3, debug_rw_st3, debug_byteen_st3, debug_tid_st3} = inst_meta_st3;
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3} = tag_st3;
end else begin
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3, debug_rw_st3, debug_byteen_st3, debug_tid_st3} = 0;
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3} = 0;
end
`endif
// Enqueue to miss reserv if it's a valid miss
wire[`REQS_BITS-1:0] req_tid_st3;
wire[`REQ_TAG_WIDTH-1:0] req_tag_st3;
wire req_rw_st3;
wire[WORD_SIZE-1:0] req_byteen_st3;
wire mshr_push_unqual = valid_st3 && (miss_st3 || force_miss_st3);
wire mshr_push_unqual = valid_st3 && mshr_push_st3;
assign mshr_push_stall = 0;
wire mshr_push = mshr_push_unqual
@@ -696,7 +701,7 @@ end
assert(!mshr_push || !mshr_full); // mmshr stall is detected before issuing new requests
end
assign {req_tag_st3, req_rw_st3, req_byteen_st3, req_tid_st3} = inst_meta_st3;
wire incoming_fill_qual_st3 = (!drsq_empty && (addr_st3 == drsq_addr_st0)) || incoming_fill_st3;
if (DRAM_ENABLE) begin
@@ -707,7 +712,7 @@ end
// push missed requests as 'ready' if it was a forced miss but actually had a hit
// or the fill request is comming for the missed block
wire mshr_init_ready_state_st3 = valid_st3 && (!miss_st3 || incoming_fill_st3);
wire mshr_init_ready_state_st3 = valid_st3 && (!miss_st3 || incoming_fill_qual_st3);
VX_miss_resrv #(
.BANK_ID (BANK_ID),
@@ -738,14 +743,7 @@ end
// enqueue
.enqueue_st3 (mshr_push),
.enqueue_addr_st3 (addr_st3),
.enqueue_wsel_st3 (wsel_st3),
.enqueue_data_st3 (writeword_st3),
.enqueue_tid_st3 (req_tid_st3),
.enqueue_tag_st3 (req_tag_st3),
.enqueue_rw_st3 (req_rw_st3),
.enqueue_byteen_st3 (req_byteen_st3),
.enqueue_is_snp_st3 (is_snp_st3),
.enqueue_snp_inv_st3(snp_inv_st3),
.enqueue_data_st3 ({writeword_st3, req_tid_st3, tag_st3, mem_rw_st3, byteen_st3, wsel_st3, is_snp_st3, snp_inv_st3}),
.enqueue_is_mshr_st3(is_mshr_st3),
.enqueue_ready_st3 (mshr_init_ready_state_st3),
.enqueue_full (mshr_full),
@@ -759,14 +757,7 @@ end
.schedule_st0 (mshr_pop),
.dequeue_valid_st0 (mshr_valid_st0),
.dequeue_addr_st0 (mshr_addr_st0),
.dequeue_wsel_st0 (mshr_wsel_st0),
.dequeue_data_st0 (mshr_writeword_st0),
.dequeue_tid_st0 (mshr_tid_st0),
.dequeue_tag_st0 (mshr_tag_st0),
.dequeue_rw_st0 (mshr_rw_st0),
.dequeue_byteen_st0 (mshr_byteen_st0),
.dequeue_is_snp_st0 (mshr_is_snp_st0),
.dequeue_snp_inv_st0(mshr_snp_inv_st0),
.dequeue_data_st0 ({mshr_writeword_st0, mshr_tid_st0, mshr_tag_st0, mshr_rw_st0, mshr_byteen_st0, mshr_wsel_st0, mshr_is_snp_st0, mshr_snp_inv_st0}),
.dequeue_st3 (mshr_dequeue_st3)
);
end else begin
@@ -775,7 +766,8 @@ end
`UNUSED_VAR (wsel_st3)
`UNUSED_VAR (writeword_st3)
`UNUSED_VAR (snp_inv_st3)
`UNUSED_VAR (req_byteen_st3)
`UNUSED_VAR (mem_rw_st3)
`UNUSED_VAR (byteen_st3)
`UNUSED_VAR (is_snp_st3)
`UNUSED_VAR (incoming_fill_st3)
assign mshr_pending_hazard_unqual_st0 = 0;
@@ -796,7 +788,7 @@ end
wire crsq_empty, crsq_full;
wire crsq_push_unqual = valid_st3 && core_req_hit_st3 && !req_rw_st3;
wire crsq_push_unqual = valid_st3 && crsq_push_st3;
assign crsq_push_stall = crsq_push_unqual && crsq_full;
wire crsq_push = crsq_push_unqual
@@ -808,13 +800,14 @@ end
wire crsq_pop = core_rsp_valid && core_rsp_ready;
wire [`REQS_BITS-1:0] crsq_tid_st3 = req_tid_st3;
wire [CORE_TAG_WIDTH-1:0] crsq_tag_st3 = CORE_TAG_WIDTH'(req_tag_st3);
wire [CORE_TAG_WIDTH-1:0] crsq_tag_st3 = CORE_TAG_WIDTH'(tag_st3);
wire [`WORD_WIDTH-1:0] crsq_data_st3 = readword_st3;
VX_generic_queue #(
.DATAW(`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE(CRSQ_SIZE),
.BUFFERED(1)
.DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE (CRSQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) core_rsp_queue (
.clk (clk),
.reset (reset),
@@ -833,11 +826,11 @@ end
wire dreq_empty, dreq_full;
wire dreq_push_unqual = valid_st3 && send_dwb_req_st3;
assign dreq_push_stall = dreq_push_unqual && dreq_full;
wire dreq_push_unqual = valid_st3 && dreq_push_st3;
assign dreq_push_stall = dreq_push_unqual && dreq_full;
wire dreq_push = dreq_push_unqual
&& (do_writeback_st3 || !incoming_fill_qual_st3)
&& !dreq_full
&& !mshr_push_stall
&& !crsq_push_stall
@@ -854,9 +847,10 @@ end
if (DRAM_ENABLE) begin
VX_generic_queue #(
.DATAW(1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH),
.SIZE(DREQ_SIZE),
.BUFFERED(1)
.DATAW (1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH),
.SIZE (DREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) dram_req_queue (
.clk (clk),
.reset (reset),
@@ -892,8 +886,7 @@ end
wire srsq_empty, srsq_full;
wire srsq_push_unqual = valid_st3 && is_snp_st3 && !force_miss_st3;
wire srsq_push_unqual = valid_st3 && srsq_push_st3;
assign srsq_push_stall = srsq_push_unqual && srsq_full;
wire srsq_push = srsq_push_unqual
@@ -904,13 +897,14 @@ end
wire srsq_pop = snp_rsp_valid && snp_rsp_ready;
wire [SNP_TAG_WIDTH-1:0] srsq_tag_st3 = SNP_TAG_WIDTH'(req_tag_st3);
wire [SNP_TAG_WIDTH-1:0] srsq_tag_st3 = SNP_TAG_WIDTH'(tag_st3);
if (FLUSH_ENABLE) begin
VX_generic_queue #(
.DATAW (SNP_TAG_WIDTH),
.SIZE (SRSQ_SIZE),
.BUFFERED(1)
.DATAW (SNP_TAG_WIDTH),
.SIZE (SRSQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) snp_rsp_queue (
.clk (clk),
.reset (reset),
@@ -945,14 +939,14 @@ end
`SCOPE_ASSIGN (valid_st1, valid_st1);
`SCOPE_ASSIGN (valid_st2, valid_st2);
`SCOPE_ASSIGN (valid_st3, valid_st3);
`SCOPE_ASSIGN (is_fill_st0, is_fill_st0);
`SCOPE_ASSIGN (is_snp_st0, is_snp_st0);
`SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0);
`SCOPE_ASSIGN (miss_st1, miss_st1);
`SCOPE_ASSIGN (dirty_st1, dirty_st1);
`SCOPE_ASSIGN (miss_st1, miss_st1);
`SCOPE_ASSIGN (dirty_st1, dirty_st1);
`SCOPE_ASSIGN (force_miss_st1, force_miss_st1);
`SCOPE_ASSIGN (mshr_push, mshr_push);
`SCOPE_ASSIGN (pipeline_stall, pipeline_stall);
`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID));
`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
`SCOPE_ASSIGN (addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
@@ -961,8 +955,8 @@ end
`ifdef PERF_ENABLE
assign perf_pipe_stall = pipeline_stall;
assign perf_mshr_stall = mshr_going_full;
assign perf_read_miss = !pipeline_stall & miss_st1 & !is_mshr_st1 & !mem_rw_st1;
assign perf_write_miss = !pipeline_stall & miss_st1 & !is_mshr_st1 & mem_rw_st1;
assign perf_read_miss = !pipeline_stall & miss_st2 & !is_mshr_st2 & !mem_rw_st2;
assign perf_write_miss = !pipeline_stall & miss_st2 & !is_mshr_st2 & mem_rw_st2;
if (DRAM_ENABLE) begin
assign perf_evict = dreq_push & do_writeback_st3 & !is_snp_st3;
end else begin

126
hw/rtl/cache/VX_bank_core_req_queue.v vendored
View File

@@ -22,7 +22,7 @@ module VX_bank_core_req_queue #(
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr_in,
input wire [`CORE_REQ_TAG_COUNT-1:0] rw_in,
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen_in,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] writedata_in,
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] wdata_in,
// Dequeue
input wire pop,
@@ -30,7 +30,7 @@ module VX_bank_core_req_queue #(
output wire [`WORD_ADDR_WIDTH-1:0] addr_out,
output wire rw_out,
output wire [WORD_SIZE-1:0] byteen_out,
output wire [`WORD_WIDTH-1:0] writedata_out,
output wire [`WORD_WIDTH-1:0] wdata_out,
output wire [`REQS_BITS-1:0] tid_out,
// States
@@ -43,7 +43,7 @@ module VX_bank_core_req_queue #(
wire [`CORE_REQ_TAG_COUNT-1:0] q_rw;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] q_byteen;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] q_addr;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] q_writedata;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] q_wdata;
wire q_push;
wire q_pop;
wire q_empty;
@@ -56,16 +56,17 @@ module VX_bank_core_req_queue #(
end
VX_generic_queue #(
.DATAW($bits(valids_in) + $bits(tag_in) + $bits(addr_in) + $bits(rw_in) + $bits(byteen_in) + $bits(writedata_in)),
.SIZE(CREQ_SIZE),
.BUFFERED(1)
.DATAW ($bits(valids_in) + $bits(tag_in) + $bits(addr_in) + $bits(rw_in) + $bits(byteen_in) + $bits(wdata_in)),
.SIZE (CREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) req_queue (
.clk (clk),
.reset (reset),
.push (q_push),
.pop (q_pop),
.data_in ({valids_in, tag_in, addr_in, rw_in, byteen_in, writedata_in}),
.data_out ({q_valids, q_tag, q_addr, q_rw, q_byteen, q_writedata}),
.data_in ({valids_in, tag_in, addr_in, rw_in, byteen_in, wdata_in}),
.data_out ({q_valids, q_tag, q_addr, q_rw, q_byteen, q_wdata}),
.empty (q_empty),
.full (q_full),
`UNUSED_PIN (size)
@@ -78,37 +79,42 @@ module VX_bank_core_req_queue #(
reg [`WORD_ADDR_WIDTH-1:0] sel_addr, sel_addr_r;
reg sel_rw, sel_rw_r;
reg [WORD_SIZE-1:0] sel_byteen, sel_byteen_r;
reg [`WORD_WIDTH-1:0] sel_writedata, sel_writedata_r;
reg [`WORD_WIDTH-1:0] sel_wdata, sel_wdata_r;
reg [$clog2(NUM_REQS+1)-1:0] q_valids_cnt_r;
wire [$clog2(NUM_REQS+1)-1:0] q_valids_cnt_n;
wire [$clog2(NUM_REQS+1)-1:0] q_valids_cnt;
reg [NUM_REQS-1:0] pop_mask;
reg fast_track;
reg [NUM_REQS-1:0] pop_mask;
reg fast_track;
wire fast_track_n;
reg req_eop; // request end of packet
reg empty_r;
assign q_push = push;
assign q_pop = pop && (q_valids_cnt_r == 1 || q_valids_cnt_r == 2) && !fast_track;
assign q_pop = pop && req_eop;
wire [NUM_REQS-1:0] requests = q_valids & ~pop_mask;
always @(*) begin
sel_idx = 0;
sel_tag = 'x;
sel_addr = 'x;
sel_rw = 'x;
sel_byteen = 'x;
sel_writedata = 'x;
sel_idx = 0;
sel_tag = 'x;
sel_addr = 'x;
sel_rw = 'x;
sel_byteen = 'x;
sel_wdata = 'x;
for (integer i = 0; i < NUM_REQS; i++) begin
if (requests[i]) begin
sel_idx = `REQS_BITS'(i);
sel_addr = q_addr[i];
if (0 == CORE_TAG_ID_BITS) begin
sel_tag = q_tag[i];
sel_rw = q_rw[i];
sel_tag = q_tag[i];
sel_rw = q_rw[i];
end
sel_byteen = q_byteen[i];
sel_writedata = q_writedata[i];
sel_byteen = q_byteen[i];
sel_wdata = q_wdata[i];
break;
end
end
@@ -121,33 +127,43 @@ module VX_bank_core_req_queue #(
.count (q_valids_cnt)
);
assign fast_track_n = (!q_empty && (empty_r || (pop && fast_track))) ? 0 :
pop ? (q_valids_cnt_r == 2) :
fast_track;
assign q_valids_cnt_n = (!q_empty && (empty_r || (pop && fast_track))) ? q_valids_cnt :
pop ? (q_valids_cnt_r - 1) :
q_valids_cnt_r;
always @(posedge clk) begin
if (reset) begin
pop_mask <= 0;
fast_track <= 0;
q_valids_cnt_r <= 0;
req_eop <= 0;
empty_r <= 1;
end else begin
if (!q_empty
&& ((0 == q_valids_cnt_r) || (pop && fast_track))) begin
q_valids_cnt_r <= q_valids_cnt;
pop_mask <= (NUM_REQS'(1) << sel_idx);
fast_track <= 0;
&& (empty_r || (pop && fast_track))) begin
pop_mask <= (NUM_REQS'(1) << sel_idx);
end else if (pop) begin
q_valids_cnt_r <= q_valids_cnt_r - 1;
fast_track <= (q_valids_cnt_r == 2);
if (q_valids_cnt_r == 1 || q_valids_cnt_r == 2) begin
if (q_valids_cnt_r == 1 || q_valids_cnt_r == 2) begin
pop_mask <= 0;
end else begin
pop_mask[sel_idx] <= 1;
end
end
q_valids_cnt_r <= q_valids_cnt_n;
fast_track <= fast_track_n;
req_eop <= (q_valids_cnt_n == 1 || q_valids_cnt_n == 2) && !fast_track_n;
empty_r <= (0 == q_valids_cnt_n);
end
if ((0 == q_valids_cnt_r) || pop) begin
sel_idx_r <= sel_idx;
sel_byteen_r <= sel_byteen;
sel_addr_r <= sel_addr;
sel_writedata_r <= sel_writedata;
if (empty_r || pop) begin
sel_idx_r <= sel_idx;
sel_byteen_r <= sel_byteen;
sel_addr_r <= sel_addr;
sel_wdata_r <= sel_wdata;
end
end
@@ -155,45 +171,45 @@ module VX_bank_core_req_queue #(
`UNUSED_VAR (sel_tag)
`UNUSED_VAR (sel_rw)
always @(posedge clk) begin
if ((0 == q_valids_cnt_r) || pop) begin
if (empty_r || pop) begin
sel_tag_r <= q_tag;
sel_rw_r <= q_rw;
end
end
end else begin
always @(posedge clk) begin
if ((0 == q_valids_cnt_r) || pop) begin
if (empty_r || pop) begin
sel_tag_r <= sel_tag;
sel_rw_r <= sel_rw;
end
end
end
assign tag_out = sel_tag_r;
assign addr_out = sel_addr_r;
assign rw_out = sel_rw_r;
assign byteen_out = sel_byteen_r;
assign writedata_out = sel_writedata_r;
assign tid_out = sel_idx_r;
assign tag_out = sel_tag_r;
assign addr_out = sel_addr_r;
assign rw_out = sel_rw_r;
assign byteen_out = sel_byteen_r;
assign wdata_out = sel_wdata_r;
assign tid_out = sel_idx_r;
assign empty = (0 == q_valids_cnt_r);
assign full = q_full;
assign full = q_full;
assign empty = empty_r;
end else begin
`UNUSED_VAR (q_valids)
assign q_push = push;
assign q_pop = pop;
assign q_push = push;
assign q_pop = pop;
assign tag_out = q_tag;
assign addr_out = q_addr;
assign rw_out = q_rw;
assign byteen_out = q_byteen;
assign writedata_out = q_writedata;
assign tid_out = 0;
assign tag_out = q_tag;
assign addr_out = q_addr;
assign rw_out = q_rw;
assign byteen_out = q_byteen;
assign wdata_out = q_wdata;
assign tid_out = 0;
assign empty = q_empty;
assign full = q_full;
assign empty = q_empty;
assign full = q_full;
end
endmodule

12
hw/rtl/cache/VX_cache.v vendored
View File

@@ -378,9 +378,9 @@ module VX_cache #(
end
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + BANK_LINE_SIZE + `BANK_LINE_WIDTH),
.BUFFERED (1)
) dram_req_arb (
.clk (clk),
.reset (reset),
@@ -408,9 +408,9 @@ module VX_cache #(
if (FLUSH_ENABLE) begin
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.OUT_BUFFER (NUM_BANKS >= 4)
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.BUFFERED (1)
) snp_rsp_arb (
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -15,7 +15,7 @@
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// data metadata word_sel is_snp snp_inv
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
`define BANK_BITS `LOG2UP(NUM_BANKS)

33
hw/rtl/cache/VX_data_access.v vendored
View File

@@ -40,25 +40,25 @@ module VX_data_access #(
`IGNORE_WARNINGS_END
input wire writeen_in,
input wire is_fill_in,
input wire[`WORD_WIDTH-1:0] writeword_in,
input wire[`BANK_LINE_WIDTH-1:0] writedata_in,
input wire[WORD_SIZE-1:0] byteen_in,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_in,
input wire [`WORD_WIDTH-1:0] writeword_in,
input wire [`BANK_LINE_WIDTH-1:0] writedata_in,
input wire [WORD_SIZE-1:0] byteen_in,
input wire [`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_in,
// Outputs
output wire[`WORD_WIDTH-1:0] readword_out,
output wire[`BANK_LINE_WIDTH-1:0] readdata_out,
output wire[BANK_LINE_SIZE-1:0] dirtyb_out
output wire [`BANK_LINE_WIDTH-1:0] readdata_out,
output wire [BANK_LINE_SIZE-1:0] dirtyb_out
);
wire[BANK_LINE_SIZE-1:0] read_dirtyb_out;
wire[`BANK_LINE_WIDTH-1:0] read_data;
wire [BANK_LINE_SIZE-1:0] read_dirtyb_out;
wire [`BANK_LINE_WIDTH-1:0] read_data;
wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
wire write_enable;
wire[`BANK_LINE_WIDTH-1:0] write_data;
wire [`BANK_LINE_WIDTH-1:0] write_data;
wire[`LINE_SELECT_BITS-1:0] addrline = addr_in[`LINE_SELECT_BITS-1:0];
wire [`LINE_SELECT_BITS-1:0] addrline = addr_in[`LINE_SELECT_BITS-1:0];
VX_data_store #(
.CACHE_SIZE (CACHE_SIZE),
@@ -68,7 +68,6 @@ module VX_data_access #(
.WRITE_ENABLE (WRITE_ENABLE)
) data_store (
.clk (clk),
.reset (reset),
.read_addr (addrline),
@@ -81,7 +80,7 @@ module VX_data_access #(
.write_addr (addrline),
.write_data (write_data)
);
if (`WORD_SELECT_WIDTH != 0) begin
wire [`WORD_WIDTH-1:0] readword = read_data[wordsel_in * `WORD_WIDTH +: `WORD_WIDTH];
for (genvar i = 0; i < WORD_SIZE; i++) begin
@@ -97,16 +96,12 @@ module VX_data_access #(
wire word_sel = (`WORD_SELECT_WIDTH == 0) || (wordsel_in == `UP(`WORD_SELECT_WIDTH)'(i));
assign byte_enable[i] = is_fill_in ? {WORD_SIZE{1'b1}} :
word_sel ? byteen_in :
{WORD_SIZE{1'b0}};
word_sel ? byteen_in : {WORD_SIZE{1'b0}};
assign write_data[i * `WORD_WIDTH +: `WORD_WIDTH] = is_fill_in ? writedata_in[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_in;
end
assign write_enable = valid_in
&& writeen_in
&& !stall;
assign write_enable = valid_in && writeen_in && !stall;
assign dirtyb_out = read_dirtyb_out;
assign readdata_out = read_data;

1
hw/rtl/cache/VX_data_store.v vendored
View File

@@ -46,7 +46,6 @@ module VX_data_store #(
.DATAW(BANK_LINE_SIZE * 8),
.SIZE(`BANK_LINE_COUNT),
.BYTEENW(BANK_LINE_SIZE),
.BUFFERED(0),
.RWCHECK(1)
) data (
.clk(clk),

33
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -39,36 +39,22 @@ module VX_miss_resrv #(
// enqueue
input wire enqueue_st3,
input wire[`LINE_ADDR_WIDTH-1:0] enqueue_addr_st3,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] enqueue_wsel_st3,
input wire[`WORD_WIDTH-1:0] enqueue_data_st3,
input wire[`REQS_BITS-1:0] enqueue_tid_st3,
input wire[`REQ_TAG_WIDTH-1:0] enqueue_tag_st3,
input wire enqueue_rw_st3,
input wire[WORD_SIZE-1:0] enqueue_byteen_st3,
input wire enqueue_is_snp_st3,
input wire enqueue_snp_inv_st3,
input wire [`LINE_ADDR_WIDTH-1:0] enqueue_addr_st3,
input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data_st3,
input wire enqueue_is_mshr_st3,
input wire enqueue_ready_st3,
output wire enqueue_full,
// fill
input wire update_ready_st0,
input wire[`LINE_ADDR_WIDTH-1:0] addr_st0,
input wire [`LINE_ADDR_WIDTH-1:0] addr_st0,
output wire pending_hazard_st0,
// dequeue
input wire schedule_st0,
output wire dequeue_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] dequeue_addr_st0,
output wire[`UP(`WORD_SELECT_WIDTH)-1:0] dequeue_wsel_st0,
output wire[`WORD_WIDTH-1:0] dequeue_data_st0,
output wire[`REQS_BITS-1:0] dequeue_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] dequeue_tag_st0,
output wire dequeue_rw_st0,
output wire[WORD_SIZE-1:0] dequeue_byteen_st0,
output wire dequeue_is_snp_st0,
output wire dequeue_snp_inv_st0,
output wire [`LINE_ADDR_WIDTH-1:0] dequeue_addr_st0,
output wire [`MSHR_DATA_WIDTH-1:0] dequeue_data_st0,
input wire dequeue_st3
);
reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
@@ -76,8 +62,7 @@ module VX_miss_resrv #(
reg [MSHR_SIZE-1:0] valid_table;
reg [MSHR_SIZE-1:0] ready_table;
reg [`LOG2UP(MSHR_SIZE)-1:0] schedule_ptr, restore_ptr;
reg [`LOG2UP(MSHR_SIZE)-1:0] head_ptr;
reg [`LOG2UP(MSHR_SIZE)-1:0] tail_ptr;
reg [`LOG2UP(MSHR_SIZE)-1:0] head_ptr, tail_ptr;
reg [`LOG2UP(MSHR_SIZE+1)-1:0] size;
assign enqueue_full = (size == $bits(size)'(MSHR_SIZE));
@@ -151,8 +136,6 @@ module VX_miss_resrv #(
VX_dp_ram #(
.DATAW(`MSHR_DATA_WIDTH),
.SIZE(MSHR_SIZE),
.BYTEENW(1),
.BUFFERED(0),
.RWCHECK(1)
) datatable (
.clk(clk),
@@ -161,8 +144,8 @@ module VX_miss_resrv #(
.wren(mshr_push),
.byteen(1'b1),
.rden(1'b1),
.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
.dout({dequeue_data_st0, dequeue_tid_st0, dequeue_tag_st0, dequeue_rw_st0, dequeue_byteen_st0, dequeue_wsel_st0, dequeue_is_snp_st0, dequeue_snp_inv_st0})
.din(enqueue_data_st3),
.dout(dequeue_data_st0)
);
`ifdef DBG_PRINT_CACHE_MSHR

101
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -7,7 +7,8 @@ module VX_snp_forwarder #(
parameter NUM_REQS = 1,
parameter SREQ_SIZE = 1,
parameter TAG_IN_WIDTH = 1,
parameter TAG_OUT_WIDTH = `LOG2UP(SREQ_SIZE)
parameter TAG_OUT_WIDTH = `LOG2UP(SREQ_SIZE),
parameter BUFFERED = 0
) (
input wire clk,
input wire reset,
@@ -23,7 +24,7 @@ module VX_snp_forwarder #(
output wire snp_rsp_valid,
output wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr,
output wire snp_rsp_inv,
output wire [TAG_IN_WIDTH-1:0] snp_rsp_tag,
output wire [TAG_IN_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// Snoop Forwarding out
@@ -45,6 +46,11 @@ module VX_snp_forwarder #(
if (NUM_REQS > 1) begin
reg [REQ_QUAL_BITS:0] pending_cntrs [SREQ_SIZE-1:0];
wire [TAG_IN_WIDTH-1:0] snp_rsp_tag_unqual;
wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr_unqual;
wire snp_rsp_inv_unqual;
wire snp_rsp_ready_unqual;
wire [TAG_OUT_WIDTH-1:0] sfq_write_addr, sfq_read_addr;
wire sfq_full;
@@ -52,30 +58,31 @@ module VX_snp_forwarder #(
wire [TAG_OUT_WIDTH-1:0] fwdin_tag;
wire fwdin_valid;
wire fwdin_ready = snp_rsp_ready || (1 != pending_cntrs[sfq_read_addr]);
wire fwdin_ready = snp_rsp_ready_unqual || (1 != pending_cntrs[sfq_read_addr]);
wire fwdin_fire = fwdin_valid && fwdin_ready;
assign snp_rsp_valid = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]);
wire snp_rsp_valid_unqual = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]);
assign sfq_read_addr = fwdin_tag;
wire sfq_acquire = snp_req_valid && snp_req_ready;
wire sfq_release = snp_rsp_valid && snp_rsp_ready;
wire sfq_release = snp_rsp_valid_unqual && snp_rsp_ready_unqual;
VX_cam_buffer #(
.DATAW (SRC_ADDR_WIDTH + 1 + TAG_IN_WIDTH),
.SIZE (SREQ_SIZE)
.DATAW (SRC_ADDR_WIDTH + 1 + TAG_IN_WIDTH),
.SIZE (SREQ_SIZE),
.FASTRAM (1)
) req_metadata_buf (
.clk (clk),
.reset (reset),
.write_addr (sfq_write_addr),
.acquire_slot (sfq_acquire),
.read_addr (sfq_read_addr),
.write_data ({snp_req_addr, snp_req_inv, snp_req_tag}),
.read_data ({snp_rsp_addr, snp_rsp_inv, snp_rsp_tag}),
.release_addr (sfq_read_addr),
.release_slot (sfq_release),
.full (sfq_full)
.clk (clk),
.reset (reset),
.write_addr (sfq_write_addr),
.acquire_slot (sfq_acquire),
.read_addr (sfq_read_addr),
.write_data ({snp_req_tag, snp_req_addr, snp_req_inv}),
.read_data ({snp_rsp_tag_unqual, snp_rsp_addr_unqual, snp_rsp_inv_unqual}),
.release_addr (sfq_read_addr),
.release_slot (sfq_release),
.full (sfq_full)
);
wire fwdout_valid;
@@ -115,21 +122,21 @@ module VX_snp_forwarder #(
fwdout_tag_r <= sfq_write_addr;
end
end
assign fwdout_valid = dispatch_hold_r || (snp_req_valid && !sfq_full);
assign fwdout_tag = dispatch_hold_r ? fwdout_tag_r : sfq_write_addr;
assign fwdout_addr = dispatch_hold_r ? fwdout_addr_r : {snp_req_addr, ADDR_DIFF'(0)};
assign fwdout_inv = dispatch_hold_r ? fwdout_inv_r : snp_req_inv;
assign dispatch_hold= dispatch_hold_r;
assign fwdout_valid = dispatch_hold_r || (snp_req_valid && !sfq_full);
assign fwdout_tag = dispatch_hold_r ? fwdout_tag_r : sfq_write_addr;
assign fwdout_addr = dispatch_hold_r ? fwdout_addr_r : {snp_req_addr, ADDR_DIFF'(0)};
assign fwdout_inv = dispatch_hold_r ? fwdout_inv_r : snp_req_inv;
assign dispatch_hold = dispatch_hold_r;
end else begin
assign fwdout_valid = snp_req_valid && !sfq_full;
assign fwdout_tag = sfq_write_addr;
assign fwdout_addr = snp_req_addr;
assign fwdout_inv = snp_req_inv;
assign dispatch_hold= 1'b0;
assign fwdout_valid = snp_req_valid && !sfq_full;
assign fwdout_tag = sfq_write_addr;
assign fwdout_addr = snp_req_addr;
assign fwdout_inv = snp_req_inv;
assign dispatch_hold = 1'b0;
end
always @(posedge clk) begin
if (sfq_acquire) begin
if (sfq_acquire) begin
pending_cntrs[sfq_write_addr] <= NUM_REQUESTS_QUAL;
end
if (fwdin_fire) begin
@@ -143,7 +150,7 @@ module VX_snp_forwarder #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DST_ADDR_WIDTH + 1 + TAG_OUT_WIDTH),
.PASSTHRU (NUM_REQS >= 4)
.PASSTHRU (!BUFFERED)
) fwdout_buffer (
.clk (clk),
.reset (reset),
@@ -171,19 +178,31 @@ module VX_snp_forwarder #(
assign snp_req_ready = fwdout_ready && !sfq_full && !dispatch_hold;
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (TAG_OUT_WIDTH),
.IN_BUFFER (NUM_REQS >= 4),
.OUT_BUFFER (NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (TAG_OUT_WIDTH)
) snp_fwdin_arb (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid),
.data_in (snp_fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid),
.data_in (snp_fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)
);
VX_skid_buffer #(
.DATAW (TAG_IN_WIDTH + SRC_ADDR_WIDTH + 1),
.PASSTHRU (!BUFFERED)
) rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (snp_rsp_valid_unqual),
.data_in ({snp_rsp_tag_unqual, snp_rsp_addr_unqual, snp_rsp_inv_unqual}),
.ready_in (snp_rsp_ready_unqual),
.valid_out (snp_rsp_valid),
.data_out ({snp_rsp_tag, snp_rsp_addr, snp_rsp_inv}),
.ready_out (snp_rsp_ready)
);
`ifdef DBG_PRINT_CACHE_SNP

2
hw/rtl/cache/VX_tag_access.v vendored
View File

@@ -54,7 +54,7 @@ module VX_tag_access #(
wire read_valid;
wire read_dirty;
wire[`TAG_SELECT_BITS-1:0] read_tag;
wire [`TAG_SELECT_BITS-1:0] read_tag;
wire do_fill;
wire do_write;

2
hw/rtl/cache/VX_tag_store.v vendored
View File

@@ -48,8 +48,6 @@ module VX_tag_store #(
VX_dp_ram #(
.DATAW(`TAG_SELECT_BITS),
.SIZE(`BANK_LINE_COUNT),
.BYTEENW(1),
.BUFFERED(0),
.RWCHECK(1)
) tags (
.clk(clk),