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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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20
hw/rtl/afu/VX_avs_wrapper.v
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@@ -59,20 +59,25 @@ module VX_avs_wrapper #(
+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
reg rsp_queue_ready;
always @(posedge clk) begin
if (reset) begin
avs_burstcount_r <= 1;
avs_bankselect_r <= 0;
avs_pending_reads <= 0;
rsp_queue_ready <= 1;
end else begin
avs_pending_reads <= avs_pending_reads_n;
rsp_queue_ready <= (avs_pending_reads_n != RD_QUEUE_SIZE);
end
end
VX_generic_queue #(
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED(1),
.FASTRAM (1)
) rd_req_queue (
.clk (clk),
.reset (reset),
@@ -86,9 +91,10 @@ module VX_avs_wrapper #(
);
VX_generic_queue #(
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED(1),
.FASTRAM (1)
) rd_rsp_queue (
.clk (clk),
.reset (reset),
@@ -101,8 +107,6 @@ module VX_avs_wrapper #(
`UNUSED_PIN (size)
);
wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
assign avs_address = dram_req_addr;