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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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hw/rtl/VX_platform.vh
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@@ -51,7 +51,7 @@
///////////////////////////////////////////////////////////////////////////////
`define USE_FAST_BRAM (* ramstyle="mlab" *)
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
///////////////////////////////////////////////////////////////////////////////