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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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21
hw/rtl/VX_ipdom_stack.v
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@@ -14,13 +14,13 @@ module VX_ipdom_stack #(
output wire empty,
output wire full
);
localparam STACK_SIZE = 2 ** DEPTH;
localparam ADDRW = $clog2(DEPTH);
reg is_part [STACK_SIZE-1:0];
reg is_part [DEPTH-1:0];
reg [DEPTH-1:0] rd_ptr, wr_ptr;
reg [ADDRW-1:0] rd_ptr, wr_ptr;
wire [WIDTH - 1:0] d1, d2;
wire [WIDTH-1:0] d1, d2;
always @(posedge clk) begin
if (reset) begin
@@ -29,18 +29,17 @@ module VX_ipdom_stack #(
end else begin
if (push) begin
rd_ptr <= wr_ptr;
wr_ptr <= wr_ptr + DEPTH'(1);
wr_ptr <= wr_ptr + ADDRW'(1);
end else if (pop) begin
wr_ptr <= wr_ptr - DEPTH'(is_part[rd_ptr]);
rd_ptr <= rd_ptr - DEPTH'(is_part[rd_ptr]);
wr_ptr <= wr_ptr - ADDRW'(is_part[rd_ptr]);
rd_ptr <= rd_ptr - ADDRW'(is_part[rd_ptr]);
end
end
end
VX_dp_ram #(
.DATAW(WIDTH * 2),
.SIZE(STACK_SIZE),
.BUFFERED(0),
.SIZE(DEPTH),
.RWCHECK(0)
) store (
.clk(clk),
@@ -48,7 +47,7 @@ module VX_ipdom_stack #(
.raddr(rd_ptr),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.rden(pop),
.din({q2, q1}),
.dout({d2, d1})
);
@@ -64,6 +63,6 @@ module VX_ipdom_stack #(
assign d = p ? d1 : d2;
assign empty = ~(| wr_ptr);
assign full = ((STACK_SIZE-1) == wr_ptr);
assign full = (ADDRW'(DEPTH-1) == wr_ptr);
endmodule