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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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76
hw/rtl/VX_csr_io_arb.v
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@@ -1,24 +1,26 @@
`include "VX_define.vh"
module VX_csr_io_arb #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter BUFFERED_REQ = 0,
parameter BUFFERED_RSP = 0,
parameter DATA_SIZE = (DATA_WIDTH / 8),
parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire [LOG_NUM_REQS-1:0] request_id,
input wire [LOG_NUM_REQS-1:0] request_id,
// input requests
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
// output request
output wire [NUM_REQS-1:0] req_valid_out,
@@ -33,40 +35,38 @@ module VX_csr_io_arb #(
output wire [NUM_REQS-1:0] rsp_ready_in,
// output response
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out
);
if (NUM_REQS > 1) begin
localparam REQ_DATAW = ADDR_WIDTH + 1 + DATA_WIDTH;
localparam RSP_DATAW = DATA_WIDTH;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign req_valid_out[i] = req_valid_in && (request_id == LOG_NUM_REQS'(i));
assign req_addr_out[i] = req_addr_in;
assign req_rw_out[i] = req_rw_in;
assign req_data_out[i] = req_data_in;
end
assign req_ready_in = req_ready_out[request_id];
end else begin
`UNUSED_VAR (request_id)
assign req_valid_out = req_valid_in;
assign req_addr_out = req_addr_in;
assign req_rw_out = req_rw_in;
assign req_data_out = req_data_in;
assign req_ready_in = req_ready_out;
wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_out;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign {req_addr_out[i], req_rw_out[i], req_data_out[i]} = req_merged_data_out[i];
end
///////////////////////////////////////////////////////////////////////
VX_stream_demux #(
.NUM_REQS (NUM_REQS),
.DATAW (REQ_DATAW),
.BUFFERED (BUFFERED_REQ)
) req_demux (
.clk (clk),
.reset (reset),
.sel (request_id),
.valid_in (req_valid_in),
.data_in ({req_addr_in, req_rw_in, req_data_in}),
.ready_in (req_ready_in),
.valid_out (req_valid_out),
.data_out (req_merged_data_out),
.ready_out (req_ready_out)
);
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (DATA_WIDTH),
.IN_BUFFER (NUM_REQS >= 4),
.OUT_BUFFER (NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
) rsp_arb (
.clk (clk),
.reset (reset),